Issued Patents All Time
Showing 51–75 of 80 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7943499 | FUSI integration method using SOG as a sacrificial planarization layer | Jiong-Ping Lu, Yaw S. Obeng, Joe G. Tran | 2011-05-17 |
| 7884019 | Poison-free and low ULK damage integration scheme for damascene interconnects | William W. Dostalik, Yong-Seok Choi | 2011-02-08 |
| 7741224 | Plasma treatment and repair processes for reducing sidewall damage in low-k dielectrics | Laura M. Matz, Rosa A. Orozco-Teran | 2010-06-22 |
| 7732312 | FUSI integration method using SOG as a sacrificial planarization layer | Jiong-Ping Lu, Yaw S. Obeng, Joe G. Tran | 2010-06-08 |
| 7732313 | FUSI integration method using SOG as a sacrificial planarization layer | Jiong-Ping Lu, Yaw S. Obeng, Joe G. Tran | 2010-06-08 |
| 7698555 | System and method for enabling secure access to a program of a headless server device | Kevin Carson | 2010-04-13 |
| 7630863 | Apparatus, method, and system for wide-area protection and control using power system data having a time component associated therewith | Gregary C. Zweigle, Armando Guzman-Casillas, Charles E. Petras | 2009-12-08 |
| 7572733 | Gas switching during an etch process to modulate the characteristics of the etch | Francis G. Celii | 2009-08-11 |
| 7560385 | Etching systems and processing gas specie modulation | Francis G. Celii | 2009-07-14 |
| 7341941 | Methods to facilitate etch uniformity and selectivity | Ting Tsui, Jeannette Michelle Jacques, Robert J. Kraft | 2008-03-11 |
| 7338888 | Method for manufacturing a semiconductor device having a silicided gate electrode and a method for manufacturing an integrated circuit including the same | Jiong-Ping Lu, Haowen Bu, Shaofeng Yu | 2008-03-04 |
| 7300878 | Gas switching during an etch process to modulate the characteristics of the etch | Francis G. Celii | 2007-11-27 |
| 7282436 | Plasma treatment for silicon-based dielectrics | Hyesook Hong, Ting Tsui, Robert J. Kraft | 2007-10-16 |
| 7252941 | Expression profiling based on histocultures | Mingxu Xu, Yuying Tan | 2007-08-07 |
| 7214609 | Methods for forming single damascene via or trench cavities and for forming dual damascene via cavities | Rob Kraft, Guoqiang Xing, Karen Kirmse, Eden Zielinski | 2007-05-08 |
| 7183187 | Integration scheme for using silicided dual work function metal gates | Jiong-Ping Lu, Gregory B. Shinn | 2007-02-27 |
| 7148143 | Semiconductor device having a fully silicided gate electrode and method of manufacture therefor | Haowen Bu, Jiong-Ping Lu, Shaofeng Yu, Clint Montgomery | 2006-12-12 |
| 7129162 | Dual cap layer in damascene interconnection processes | Hyesook Hong, Guoqiang Xing | 2006-10-31 |
| 6905831 | Real time measurement of cellular responses | Mingxu Xu, Meng Yang | 2005-06-14 |
| 6900123 | BARC etch comprising a selective etch chemistry and a high polymerizing gas for CD control | Robert J. Kraft, Mark H. Somervell | 2005-05-31 |
| 6797633 | In-situ plasma ash/treatment after via etch of low-k films for poison-free dual damascene trench patterning | Robert J. Kraft, Kenneth Newton, Daty M. Rogers | 2004-09-28 |
| 6645781 | Method to determine a complete etch in integrated devices | Heungsoo Park | 2003-11-11 |
| 6642518 | Assembly and method for improved scanning electron microscope analysis of semiconductor devices | Fred Y. Clark, James D. Krouse, Robyn R. Carlson | 2003-11-04 |
| 6620560 | Plasma treatment of low-k dielectric films to improve patterning | Guoqiang Xing, Andrew John McKerrow, Robert J. Kraft, Hyesook Hong | 2003-09-16 |
| 6455411 | Defect and etch rate control in trench etch for dual damascene patterning of low-k dielectrics | Francis G. Celii, Kenneth Newton, Hiromi Sakima | 2002-09-24 |