Issued Patents All Time
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9721828 | Method to reduce particles during STI fill and reduce CMP scratches | Andrew NELSON, Richard A. Stice | 2017-08-01 |
| 9035399 | Structure for facilitating the simultaneous silicidation of a polysilicon gate and source/drain of a semiconductor device | Freidoon Mehrad, Shaofeng Yu, Steven A. Vitale | 2015-05-19 |
| 7998865 | Systems and methods for removing wafer edge residue and debris using a residue remover mechanism | Brian K. Kirkpatrick, Alfred Griffin | 2011-08-16 |
| 7943499 | FUSI integration method using SOG as a sacrificial planarization layer | Jiong-Ping Lu, Yaw S. Obeng, Ping Jiang | 2011-05-17 |
| 7732312 | FUSI integration method using SOG as a sacrificial planarization layer | Jiong-Ping Lu, Yaw S. Obeng, Ping Jiang | 2010-06-08 |
| 7732313 | FUSI integration method using SOG as a sacrificial planarization layer | Jiong-Ping Lu, Yaw S. Obeng, Ping Jiang | 2010-06-08 |
| 7727842 | Method of simultaneously siliciding a polysilicon gate and source/drain of a semiconductor device, and related device | Freidoon Mehrad, Shaofeng Yu, Steven A. Vitale | 2010-06-01 |
| 7498264 | Method to obtain fully silicided poly gate | Freidoon Mehard, Shafoeng Yu | 2009-03-03 |
| 7396716 | Method to obtain fully silicided poly gate | Freidoon Mehrad, Shaofeng Yu | 2008-07-08 |
| 7186651 | Chemical mechanical polishing method and apparatus | Chad Kaneshige, Brian K. Kirkpatrick | 2007-03-06 |
| 6686283 | Shallow trench isolation planarization using self aligned isotropic etch | Shawn T. Walsh, John E. Campbell, Somit Joshi, James B. Friedmann, Michael J. McGranaghan +8 more | 2004-02-03 |