Issued Patents All Time
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12406880 | Dielectric silicon nitride barrier deposition process for improved metal leakage and adhesion | Qi-Zhong Hong, Joseph Song, Bhaskar Srinivasan | 2025-09-02 |
| 11848268 | Thin film resistor with punch-through vias | Dhishan Kande, Qi-Zhong Hong, Abbas Ali | 2023-12-19 |
| 11424183 | IC with thin film resistor with metal walls | Qi-Zhong Hong, Honglin Guo, Benjamin James Timmer | 2022-08-23 |
| 11101212 | Thin film resistor with punch-through vias | Dhishan Kande, Qi-Zhong Hong, Abbas Ali | 2021-08-24 |
| 10956646 | Customizing circuit layout design rules for fabrication facilities | Tae Seung Kim | 2021-03-23 |
| 10784193 | IC with thin film resistor with metal walls | Qi-Zhong Hong, Honglin Guo, Benjamin James Timmer | 2020-09-22 |
| 10354951 | Thin film resistor with punch-through vias | Dhishan Kande, Qi-Zhong Hong, Abbas Ali | 2019-07-16 |
| 10249621 | Dummy contacts to mitigate plasma charging damage to gate dielectrics | Mark Visokay, Tae Seung Kim, Mahalingam Nandakumar, Eric D. Rullan | 2019-04-02 |
| 8309957 | Replacement of scribeline padframe with saw-friendly design | Basab Chatterjee, Jeffrey Alan West | 2012-11-13 |
| 8093070 | Method for leakage reduction in fabrication of high-density FRAM arrays | Francis G. Celii, Kezhakkedath R. Udayakumar, Theodore S. Moise, Scott R. Summerfelt | 2012-01-10 |
| 7183187 | Integration scheme for using silicided dual work function metal gates | Jiong-Ping Lu, Ping Jiang | 2007-02-27 |
| 6821791 | Method for reworking metal layers on integrated circuit bond pads | Roger J. Stierman, Thomas M. Moore | 2004-11-23 |
| 6686283 | Shallow trench isolation planarization using self aligned isotropic etch | Shawn T. Walsh, John E. Campbell, Somit Joshi, James B. Friedmann, Michael J. McGranaghan +8 more | 2004-02-03 |
| 6534327 | Method for reworking metal layers on integrated circuit bond pads | Roger J. Stierman, Thomas M. Moore | 2003-03-18 |
| 6268297 | Self-planarizing low-temperature doped-silicate-glass process capable of gap-filling narrow spaces | Somnath Nag, Girish Dixit | 2001-07-31 |
| 5996594 | Post-chemical mechanical planarization clean-up process using post-polish scrubbing | Sudipto Ranendra Roy, Iqbal Ali, Rajani C. Shah, Shelley H. Peterman, Srini Raghavan | 1999-12-07 |
| 5751582 | Controlling process modules using site models and monitor wafer control | Sharad Saxena, Purnendu K. Mozumder, Kelly Taylor | 1998-05-12 |