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Thin film resistor with punch-through vias |
Dhishan Kande, Qi-Zhong Hong, Abbas Ali |
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Qi-Zhong Hong, Honglin Guo, Benjamin James Timmer |
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Thin film resistor with punch-through vias |
Dhishan Kande, Qi-Zhong Hong, Abbas Ali |
2021-08-24 |
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Customizing circuit layout design rules for fabrication facilities |
Tae Seung Kim |
2021-03-23 |
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IC with thin film resistor with metal walls |
Qi-Zhong Hong, Honglin Guo, Benjamin James Timmer |
2020-09-22 |
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Thin film resistor with punch-through vias |
Dhishan Kande, Qi-Zhong Hong, Abbas Ali |
2019-07-16 |
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Dummy contacts to mitigate plasma charging damage to gate dielectrics |
Mark Visokay, Tae Seung Kim, Mahalingam Nandakumar, Eric D. Rullan |
2019-04-02 |
| 8309957 |
Replacement of scribeline padframe with saw-friendly design |
Basab Chatterjee, Jeffrey Alan West |
2012-11-13 |
| 8093070 |
Method for leakage reduction in fabrication of high-density FRAM arrays |
Francis G. Celii, Kezhakkedath R. Udayakumar, Theodore S. Moise, Scott R. Summerfelt |
2012-01-10 |
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Integration scheme for using silicided dual work function metal gates |
Jiong-Ping Lu, Ping Jiang |
2007-02-27 |
| 6821791 |
Method for reworking metal layers on integrated circuit bond pads |
Roger J. Stierman, Thomas M. Moore |
2004-11-23 |
| 6686283 |
Shallow trench isolation planarization using self aligned isotropic etch |
Shawn T. Walsh, John E. Campbell, Somit Joshi, James B. Friedmann, Michael J. McGranaghan +8 more |
2004-02-03 |
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Method for reworking metal layers on integrated circuit bond pads |
Roger J. Stierman, Thomas M. Moore |
2003-03-18 |
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Self-planarizing low-temperature doped-silicate-glass process capable of gap-filling narrow spaces |
Somnath Nag, Girish Dixit |
2001-07-31 |
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Post-chemical mechanical planarization clean-up process using post-polish scrubbing |
Sudipto Ranendra Roy, Iqbal Ali, Rajani C. Shah, Shelley H. Peterman, Srini Raghavan |
1999-12-07 |
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Controlling process modules using site models and monitor wafer control |
Sharad Saxena, Purnendu K. Mozumder, Kelly Taylor |
1998-05-12 |