Issued Patents All Time
Showing 1–22 of 22 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7673262 | System and method for product yield prediction | Brian E. Stine, Christopher Hess, John Kibarian, Kimon Michaels, Joseph C. Davis +4 more | 2010-03-02 |
| 7373625 | System and method for product yield prediction | Brian E. Stine, Christopher Hess, John Kibarian, Kimon Michaels, Joseph C. Davis +4 more | 2008-05-13 |
| 7356800 | System and method for product yield prediction | Brian E. Stine, Christopher Hess, John Kibarian, Kimon Michaels, Joseph C. Davis +4 more | 2008-04-08 |
| 7174521 | System and method for product yield prediction | Brian E. Stine, Christopher Hess, John Kibarian, Kimon Michaels, Joseph C. Davis +4 more | 2007-02-06 |
| 6901564 | System and method for product yield prediction | Brian E. Stine, Christopher Hess, John Kibarian, Kimon Michaels, Joseph C. Davis +4 more | 2005-05-31 |
| 6438439 | Equipment evaluation and design | Gabriel G. Barna, Joseph C. Davis, Richard G. Burch | 2002-08-20 |
| 6388288 | Integrating dual supply voltages using a single extra mask level | Karthik Vasanth, Sharad Saxena, Richard G. Burch, Joseph C. Davis, Chenjing Fernando +1 more | 2002-05-14 |
| 6381564 | Method and system for using response-surface methodologies to determine optimal tuning parameters for complex simulators | Joseph C. Davis, Karthik Vasanth, Sharad Saxena, Suraj Rao, Chenjing Fernando +1 more | 2002-04-30 |
| 6317640 | System and method for non-parametric modeling of processed induced variability | Suraj Rao, Sharad Saxena, Pushkar Apte, Richard G. Burch, Karthik Vasanth +2 more | 2001-11-13 |
| 6311096 | Design of microelectronic process flows for manufacturability and performance | Sharad Saxena, Karthik Vasanth, Richard G. Burch, Suraj Rao, Joseph C. Davis | 2001-10-30 |
| 6157062 | Integrating dual supply voltage by removing the drain extender implant from the high voltage device | Karthik Vasanth, Richard G. Burch, Sharad Saxena, Chenjing Fernando, Joseph C. Davis +1 more | 2000-12-05 |
| 5912678 | Process flow design at the module effects level through the use of acceptability regions | Sharad Saxena, Amy J. Unruh, Richard G. Burch | 1999-06-15 |
| 5901062 | Semiconductor structure design and process visualization through the use of simple process models and intuitive interfaces | Richard G. Burch | 1999-05-04 |
| 5838595 | Apparatus and method for model based process control | Michael Francis Sullivan, Judith S. Hirsch, Stephanie W. Butler, Nicholas John Tovell, Jerry Stefani +3 more | 1998-11-17 |
| 5822241 | DRAM pass transistors | Amitava Chatterjee | 1998-10-13 |
| 5751582 | Controlling process modules using site models and monitor wafer control | Sharad Saxena, Gregory B. Shinn, Kelly Taylor | 1998-05-12 |
| 5661669 | Method for controlling semiconductor wafer processing | Gabe G. Barna | 1997-08-26 |
| 5548548 | Pass transistor for a 256 megabit dram with negatively biased substrate | Amitava Chatterjee, Jiann Liu, Mark S. Rodder, Ih-Chin Chen | 1996-08-20 |
| 5546312 | Use of spatial models for simultaneous control of various non-uniformity metrics | Sharad Saxena | 1996-08-13 |
| 5526293 | System and method for controlling semiconductor wafer processing | Gabe G. Barna | 1996-06-11 |
| 5408405 | Multi-variable statistical process controller for discrete manufacturing | Sharad Saxena, William W. Pu | 1995-04-18 |
| 5402367 | Apparatus and method for model based process control | Michael Francis Sullivan, Judith S. Hirsch, Stephanie W. Butler, Nicholas John Tovell, Jerry Stefani +3 more | 1995-03-28 |