Issued Patents All Time
Showing 51–75 of 126 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9842933 | Formation of bottom junction in vertical FET devices | Kwan-Yong Lim, Steven Bentley, Daniel Chanemougame | 2017-12-12 |
| 9805986 | High mobility transistors | Manoj Mehrotra, Rick L. Wise | 2017-10-31 |
| 9779946 | System and method for mitigating oxide growth in a gate dielectric | Malcolm J. Bevan, Haowen Bu, Husam N. Alshareef | 2017-10-03 |
| 9780192 | Fringe capacitance reduction for replacement gate CMOS | Mahalingam Nandakumar | 2017-10-03 |
| 9779987 | Titanium silicide formation in a narrow source-drain contact | Min Gyu Sung, Kwanyong LIM | 2017-10-03 |
| 9735111 | Dual metal-insulator-semiconductor contact structure and formulation method | Takashi Ando, Tenko Yamashita | 2017-08-15 |
| 9721796 | Methods to enhance effective work function of mid-gap metal by incorporating oxygen and hydrogen at a low thermal budget | James Joseph Chambers | 2017-08-01 |
| 9721847 | High-k / metal gate CMOS transistors with TiN gates | Brian K. Kirkpatrick | 2017-08-01 |
| 9640535 | Method for forming source/drain contacts during CMOS integration using confined epitaxial growth techniques and the resulting semiconductor devices | Ruilong Xie | 2017-05-02 |
| 9640636 | Methods of forming replacement gate structures and bottom and top source/drain regions on a vertical transistor device | Steven Bentley, John H. Zhang, Kwan-Yong Lim | 2017-05-02 |
| 9589851 | Dipole-based contact structure to reduce metal-semiconductor contact resistance in MOSFETs | Huiming Bu, Hui-feng Li, Vijay Narayanan, Tenko Yamashita | 2017-03-07 |
| 9576804 | System and method for mitigating oxide growth in a gate dielectric | Malcolm J. Bevan, Haowen Bu, Husam N. Alshareef | 2017-02-21 |
| 9543216 | Integration of hybrid germanium and group III-V contact epilayer in CMOS | Ruilong Xie | 2017-01-10 |
| 9496262 | High mobility transistors | Manoj Mehrotra, Charles Frank Machala, III, Rick L. Wise | 2016-11-15 |
| 9484255 | Hybrid source and drain contact formation using metal liner and metal insulator semiconductor contacts | Shariq Siddiqui, Tenko Yamashita | 2016-11-01 |
| 9431509 | High-K metal gate | James Joseph Chambers | 2016-08-30 |
| 9412695 | Interconnect structures and methods of fabrication | Ruilong Xie, Andreas Knorr | 2016-08-09 |
| 9397003 | Method for forming source/drain contacts during CMOS integration using confined epitaxial growth techniques | Ruilong Xie | 2016-07-19 |
| 9396951 | System and method for mitigating oxide growth in a gate dielectric | Malcolm J. Bevan, Haowen Bu, Husam N. Alshareef | 2016-07-19 |
| 9397009 | Structure and method for metal gate stack oxygen concentration control using an oxygen diffusion barrier layer and a sacrificial oxygen gettering layer | James Joseph Chambers | 2016-07-19 |
| 9397100 | Hybrid high-k first and high-k last replacement gate process | Manoj Mehrotra, Mahalingam Nandakumar | 2016-07-19 |
| 9368355 | System and method for mitigating oxide growth in a gate dielectric | Malcolm J. Bevan, Haowen Bu, Husam N. Alshareef | 2016-06-14 |
| 9356131 | Metal-gate MOS transistor and method of forming the transistor with reduced gate-to-source and gate-to-drain overlap capacitance | Manoj Mehrotra | 2016-05-31 |
| 9337297 | Fringe capacitance reduction for replacement gate CMOS | Mahalingam Nandakumar | 2016-05-10 |
| 9337044 | System and method for mitigating oxide growth in a gate dielectric | Malcolm J. Bevan, Haowen Bu, Husam N. Alshareef | 2016-05-10 |