Issued Patents All Time
Showing 25 most recent of 28 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12160219 | Metal ribs in electromechanical devices | Anindya Poddar, Masamitsu Matsuura | 2024-12-03 |
| 12154861 | Frame design in embedded die package | Woochan Kim, Masamitsu Matasuura, Mutsumi Masumoto, Kengo Aoya, Vivek Kishorechand Arora +2 more | 2024-11-26 |
| 12074134 | Package for stress sensitive component and semiconductor device | Anindya Poddar, Mahmud Halim Chowdhury, Masamitsu Matsuura, Ting-Ta Yen | 2024-08-27 |
| 12021019 | Semiconductor device package with thermal pad | Anindya Poddar, Ashok S. Prabhu, Edgar Dorotyao Balidoy, Makoto Yoshino, Ming-Yang Li | 2024-06-25 |
| 11955456 | Flip chip packaged devices with thermal pad | Anindya Poddar, Ashok S. Prabhu, Kurt Sincerbox, Makoto Shibuya | 2024-04-09 |
| 11736085 | Metal ribs in electromechanical devices | Anindya Poddar, Masamitsu Matsuura | 2023-08-22 |
| 11450638 | Bump bond structure for enhanced electromigration performance | Dibyajat Mishra, Ashok S. Prabhu, Tomoko Noguchi, Luu Thanh Nguyen, Anindya Poddar +1 more | 2022-09-20 |
| 11410875 | Fan-out electronic device | Woochan Kim, Yi Yan, Luu Thanh Nguyen, Ashok S. Prabhu, Anindya Poddar +3 more | 2022-08-09 |
| 11367699 | Integrated circuit backside metallization | Hiroyuki Sada, Shoichi Iriguchi, Genki Yano, Luu Thanh Nguyen, Ashok S. Prabhu +2 more | 2022-06-21 |
| 11183441 | Stress buffer layer in embedded package | Woochan Kim, Masamitsu Matsuura, Mutsumi Masumoto, Kengo Aoya, Vivek Kishorechand Arora +1 more | 2021-11-23 |
| 11158595 | Embedded die package multichip module | Woochan Kim, Masamitsu Matsuura, Mutsumi Masumoto, Kengo Aoya, Vivek Kishorechand Arora +1 more | 2021-10-26 |
| 10763230 | Integrated circuit backside metallization | Hiroyuki Sada, Shoichi Iriguchi, Genki Yano, Luu Thanh Nguyen, Ashok S. Prabhu +2 more | 2020-09-01 |
| 10763231 | Bump bond structure for enhanced electromigration performance | Dibyajat Mishra, Ashok S. Prabhu, Tomoko Noguchi, Luu Thanh Nguyen, Anindya Poddar +1 more | 2020-09-01 |
| 10580715 | Stress buffer layer in embedded package | Woochan Kim, Masamitsu Matsuura, Mutsumi Masumoto, Kengo Aoya, Vivek Kishorechand Arora +1 more | 2020-03-03 |
| 10573582 | Semiconductor systems having dual leadframes | Rajeev Joshi, Anindya Poddar, Ken Pham | 2020-02-25 |
| 10541220 | Printed repassivation for wafer chip scale packaging | Daiki Komatsu, Makoto Shibuya, Yi Yan, Luu Thanh Nguyen, Anindya Poddar | 2020-01-21 |
| 10312184 | Semiconductor systems having premolded dual leadframes | Rajeev Joshi, Anindya Poddar, Ken Pham | 2019-06-04 |
| 9663357 | Open cavity package using chip-embedding technology | Jie Mao, Luu Thanh Nguyen, Anindya Poddar | 2017-05-30 |
| 8389334 | Foil-based method for packaging intergrated circuits | Aninyda Poddar, Nghia Thuc Tu | 2013-03-05 |
| 7812462 | Conductive paths for transmitting an electrical signal through an electrical connector | Stephen Gee | 2010-10-12 |
| 7755200 | Methods and arrangements for forming solder joint connections | — | 2010-07-13 |
| 7629246 | High strength solder joint formation method for wafer level packages and flip applications | Viraj A. Patwardhan | 2009-12-08 |
| 7510908 | Method to dispense light blocking material for wafer level CSP | Nikhil Vishwanath Kelkar | 2009-03-31 |
| 7423337 | Integrated circuit device package having a support coating for improved reliability during temperature cycling | Viraj A. Patwardhan, Nikhil Kelkar, Shahram Mostafazadeh | 2008-09-09 |
| 7413927 | Apparatus for forming a pre-applied underfill adhesive layer for semiconductor wafer level chip-scale packages | Viraj A. Patwardhan, Nikhil Kelkar | 2008-08-19 |