Issued Patents All Time
Showing 26–50 of 71 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8084787 | PMD liner nitride films and fabrication methods for improved NMOS performance | Rajesh Khamankar, Douglas T. Grider | 2011-12-27 |
| 8053296 | Capacitor formed on a recrystallized polysilicon layer | Jiong-Ping Lu, Clint Montgomery | 2011-11-08 |
| 7939400 | Systems and methods that selectively modify liner induced stress | Ting Tsui, Satyavolu S. Papa Rao, Robert J. Kraft | 2011-05-10 |
| 7932139 | Methodology of improving the manufacturability of laser anneal | Amitabh Jain | 2011-04-26 |
| 7906441 | System and method for mitigating oxide growth in a gate dielectric | Malcolm J. Bevan, Hiroaki Niimi, Husam N. Alshareef | 2011-03-15 |
| 7897513 | Method for forming a metal silicide | Shashank S. Ekbote, Juanita DeLoach | 2011-03-01 |
| 7855111 | Border region defect reduction in hybrid orientation technology (HOT) direct silicon bonded (DSB) substrates | Shaofeng Yu, Angelo Pinto, Ajith Varghese | 2010-12-21 |
| 7847401 | Methods, systems and structures for forming semiconductor structures incorporating high-temperature processing steps | P R Chidambaram, Rajesh Khamankar, Douglas T. Grider | 2010-12-07 |
| 7795122 | Antimony ion implantation for semiconductor components | Amitabh Jain, Srinivasan Chakravarthi, Shashank S. Ekbote | 2010-09-14 |
| 7790561 | Gate sidewall spacer and method of manufacture therefor | Richard P. Rouse, Shashank S. Ekbote | 2010-09-07 |
| 7700467 | Methodology of implementing ultra high temperature (UHT) anneal in fabricating devices that contain sige | Scott Bushman, Periannan Chidambaram | 2010-04-20 |
| 7670892 | Nitrogen based implants for defect reduction in strained silicon | Srinivasan Chakravarthi, PR Chidambaram, Rajesh Khamankar, Douglas T. Grider | 2010-03-02 |
| 7667275 | Using oxynitride spacer to reduce parasitic capacitance in CMOS devices | Yuanning Chen, Kaiping Liu | 2010-02-23 |
| 7601575 | Integration of pre-S/D anneal selective nitride/oxide composite cap for improving transistor performance | Shashank S. Ekbote, Rajesh Khamankar, Shaoping Tang, Freidoon Mehrad | 2009-10-13 |
| 7572716 | Semiconductor doping with improved activation | Shashank S. Ekbote, Borna J. Obradovic, Srinivasan Chakravarthi | 2009-08-11 |
| 7553718 | Methods, systems and structures for forming semiconductor structures incorporating high-temperature processing steps | Periannan Chidambaram, Rajesh Khamankar, Douglas T. Grider | 2009-06-30 |
| 7514331 | Method of manufacturing gate sidewalls that avoids recessing | Jong Shik Yoon, Amitava Chatterjee | 2009-04-07 |
| 7442597 | Systems and methods that selectively modify liner induced stress | Ting Tsui, Satyavolu S. Papa Rao, Robert J. Kraft | 2008-10-28 |
| 7429517 | CMOS transistor using high stress liner layer | Zhiqiang Wu | 2008-09-30 |
| 7402535 | Method of incorporating stress into a transistor channel by use of a backside layer | Mahalingam Nandakumar | 2008-07-22 |
| 7341933 | Method for manufacturing a silicided gate electrode using a buffer layer | Shaofeng Yu, Jiong-Ping Lu, Lindsey Hall | 2008-03-11 |
| 7338888 | Method for manufacturing a semiconductor device having a silicided gate electrode and a method for manufacturing an integrated circuit including the same | Jiong-Ping Lu, Shaofeng Yu, Ping Jiang | 2008-03-04 |
| 7306995 | Reduced hydrogen sidewall spacer oxide | Clinton L. Montgomery, Amitabh Jain | 2007-12-11 |
| 7253049 | Method for fabricating dual work function metal gates | Jiong-Ping Lu, Shaofeng Yu, Lindsey Hall, Mark Visokay | 2007-08-07 |
| 7244654 | Drive current improvement from recessed SiGe incorporation close to gate | PR Chidambaram, Douglas T. Grider, Brian Smith, Lindsey Hall | 2007-07-17 |