Issued Patents All Time
Showing 51–71 of 71 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7226834 | PMD liner nitride films and fabrication methods for improved NMOS performance | Rajesh Khamankar, Douglas T. Grider | 2007-06-05 |
| 7217626 | Transistor fabrication methods using dual sidewall spacers | PR Chidambaram, Rajesh Khamankar, Lindsey Hall | 2007-05-15 |
| 7208380 | Interface improvement by stress application during oxide growth through use of backside films | Anand Krishnan, Srinivasan Chakravarthi | 2007-04-24 |
| 7192894 | High performance CMOS transistors using PMD liner stress | Rajesh Khamankar, Douglas T. Grider | 2007-03-20 |
| 7173296 | Reduced hydrogen sidewall spacer oxide | Clinton L. Montgomery, Amitabh Jain | 2007-02-06 |
| 7157358 | Method for using a wet etch to manufacturing a semiconductor device having a silicided gate electrode and a method for manufacturing an integrated circuit including the same | Lindsey Hall, Shaofeng Yu | 2007-01-02 |
| 7148143 | Semiconductor device having a fully silicided gate electrode and method of manufacture therefor | Jiong-Ping Lu, Shaofeng Yu, Ping Jiang, Clint Montgomery | 2006-12-12 |
| 7135361 | Method for fabricating transistor gate structures and gate dielectrics thereof | Mark Visokay, Luigi Colombo, James Joseph Chambers, Antonio Luis Pacheco Rotondaro | 2006-11-14 |
| 7129127 | Integration scheme to improve NMOS with poly cap while mitigating PMOS degradation | Periannan Chidambaram, Srinivasan Chakravarthi, Rajesh Khamankar | 2006-10-31 |
| 7122435 | Methods, systems and structures for forming improved transistors | PR Chidambaram | 2006-10-17 |
| 7061058 | Forming a retrograde well in a transistor to enhance performance of the transistor | Srinivasan Chakravarthi, PR Chidambaram, Robert C. Bowen | 2006-06-13 |
| 7060579 | Increased drive current by isotropic recess etch | PR Chidambaram, Lindsey Hall | 2006-06-13 |
| 7045431 | Method for integrating high-k dielectrics in transistor devices | Antonio Rotondaro, Douglas E. Mercer, Luigi Colombo, Mark Visokay, Malcolm J. Bevan | 2006-05-16 |
| 7012028 | Transistor fabrication methods using reduced width sidewall spacers | PR Chidambaram, Rajesh Khamankar | 2006-03-14 |
| 6930007 | Integration of pre-S/D anneal selective nitride/oxide composite cap for improving transistor performance | Shashank S. Ekbote, Rajesh Khamankar, Shaoping Tang, Freidoon Mehrad | 2005-08-16 |
| 6927137 | Forming a retrograde well in a transistor to enhance performance of the transistor | Srinivasan Chakravarthi, PR Chidambaram, Robert C. Bowen | 2005-08-09 |
| 6921703 | System and method for mitigating oxide growth in a gate dielectric | Malcolm J. Bevan, Hiroaki Niimi, Husam N. Alshareef | 2005-07-26 |
| 6812073 | Source drain and extension dopant concentration | Amitabh Jain, Wayne Bather, Stephanie W. Butler | 2004-11-02 |
| 6806149 | Sidewall processes using alkylsilane precursors for MOS transistor fabrication | Malcolm J. Bevan | 2004-10-19 |
| 6743705 | Transistor with improved source/drain extension dopant concentration | Manoj Mehrotra, Amitabh Jain | 2004-06-01 |
| 6677201 | Method of fabricating thermal CVD oxynitride and BTBAS nitride sidewall spacer for metal oxide semiconductor transistors | Amitabh Jain | 2004-01-13 |