Issued Patents All Time
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11004612 | Low temperature sub-nanometer periodic stack dielectrics | Jesus Israel Mejia Silva, Chunya Wu, Deborah J. Riley, Yun Ju Lee | 2021-05-11 |
| 9048151 | Self-powered integrated circuit with photovoltaic cell | Nagarajan Sridhar | 2015-06-02 |
| 8883541 | Self-powered integrated circuit with multi-junction photovoltaic cell | Thomas Patrick Conroy, Jeffrey R. Debord, Nagarajan Sridhar | 2014-11-11 |
| 8552470 | Self-powered integrated circuit with multi-junction photovoltaic cell | Thomas Patrick Conroy, Jeffrey R. Debord, Nagarajan Sridhar | 2013-10-08 |
| 7800226 | Integrated circuit with metal silicide regions | Maxwell Lippitt, William M. Moller | 2010-09-21 |
| 7704883 | Annealing to improve edge roughness in semiconductor technology | Stephanie W. Butler | 2010-04-27 |
| 7667275 | Using oxynitride spacer to reduce parasitic capacitance in CMOS devices | Haowen Bu, Kaiping Liu | 2010-02-23 |
| 7569464 | Method for manufacturing a semiconductor device having improved across chip implant uniformity | Karen Kirmse, Jarvis Benjamin Jacobs, Deborah J. Riley | 2009-08-04 |
| 7276408 | Reduction of dopant loss in a gate structure | Mark Visokay | 2007-10-02 |
| 7250356 | Method for forming metal silicide regions in an integrated circuit | Maxwell Lippitt, William M. Moller | 2007-07-31 |
| 7148153 | Process for oxide fabrication using oxidation steps below and above a threshold temperature | Sundar Srinivasan Chetlur, Pradip K. Roy | 2006-12-12 |
| 7033897 | Encapsulated spacer with low dielectric constant material to reduce the parasitic capacitance between gate and drain in CMOS technology | Antonio Luis Pacheco Rotondaro, Karen Kirmse | 2006-04-25 |
| 6930006 | Electronic circuit structure with improved dielectric properties | Konstantin Bourdelle | 2005-08-16 |
| 6551946 | TWO-STEP OXIDATION PROCESS FOR OXIDIZING A SILICON SUBSTRATE WHEREIN THE FIRST STEP IS CARRIED OUT AT A TEMPERATURE BELOW THE VISCOELASTIC TEMPERATURE OF SILICON DIOXIDE AND THE SECOND STEP IS CARRIED OUT AT A TEMPERATURE ABOVE THE VISCOELASTIC TEMPERATURE | Sundar Srinivasan Chetlur, Pradip K. Roy | 2003-04-22 |
| 6541394 | Method of making a graded grown, high quality oxide layer for a semiconductor device | Sailesh Mansinh Merchant, Pradip K. Roy | 2003-04-01 |
| 6492712 | High quality oxide for use in integrated circuits | Sundar Srinivasan Chetlur, Sailesh Mansinh Merchant, Pradip K. Roy | 2002-12-10 |
| 6303397 | Method for benchmarking thin film measurement tools | Linette Lozada, Yi Ma, Roger M. Young | 2001-10-16 |