Issued Patents All Time
Showing 126–150 of 636 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10566310 | Microelectronic packages having stacked die and wire bond interconnects | Kyong-Mo Bang | 2020-02-18 |
| 10559494 | Microelectronic elements with post-assembly planarization | Vage Oganesian, Craig Mitchell, Ilyas Mohammed, Piyush Savalia | 2020-02-11 |
| 10535909 | Methods of forming flipped RF filter components | Shaowu Huang | 2020-01-14 |
| 10483217 | Warpage balancing in thin packages | Sangil Lee, Craig Mitchell, Gabriel Z. Guevara, Javier A. Delacruz | 2019-11-19 |
| 10475733 | Method and structures for heat dissipating interposers | Cyprian Emeka Uzoh, Pezhman Monadgemi, Terrence Caskey, Fatima Lina Ayatollahi, Charles G. Woychik +1 more | 2019-11-12 |
| 10468380 | Stackable microelectronic package structures | Kyong-Mo Bang | 2019-11-05 |
| 10460958 | Method of manufacturing embedded packaging with preformed vias | Ilyas Mohammed | 2019-10-29 |
| 10403599 | Embedded organic interposers for high bandwidth | Javier A. Delacruz | 2019-09-03 |
| 10354976 | Dies-on-package devices and methods therefor | Min Tao, Hoki Kim, Ashok S. Prabhu, Zhuowen Sun, Wael Zohni | 2019-07-16 |
| 10354942 | Staged via formation from both sides of chip | Vage Oganesian, Ilyas Mohammed, Craig Mitchell, Piyush Savalia | 2019-07-16 |
| 10347582 | Embedded vialess bridges | — | 2019-07-09 |
| 10319673 | Low CTE interposer | Kishor Desai | 2019-06-11 |
| 10304803 | Nanoscale interconnect array for stacked dies | Liang Wang, Bongsub Lee, Sangil Lee | 2019-05-28 |
| 10297582 | BVA interposer | Terrence Caskey, Ilyas Mohammed, Cyprian Emeka Uzoh, Charles G. Woychik, Michael Newman +3 more | 2019-05-21 |
| 10297570 | 3D-joining of microelectronic components with conductively self-adjusting anisotropic matrix | — | 2019-05-21 |
| 10290612 | Systems and methods for flash stacking | Ilyas Mohammed, Javier A. Delacruz | 2019-05-14 |
| 10290589 | Folding thin systems | Ilyas Mohammed | 2019-05-14 |
| 10283449 | Low stress vias | Ilyas Mohammed, Cyprian Emeka Uzoh | 2019-05-07 |
| 10283445 | Bonding of laminates with electrical interconnects | Javier A. Delacruz, Wael Zohni, Liang Wang, Akash Agrawal | 2019-05-07 |
| 10276909 | Structure comprising at least a first element bonded to a carrier having a closed metallic channel waveguide formed therein | Shaowu Huang, Javier A. Delacruz | 2019-04-30 |
| 10262947 | Active chip on carrier or laminated chip having microelectronic element embedded therein | Vage Oganesian, Ilyas Mohammed, Craig Mitchell, Piyush Savalia | 2019-04-16 |
| 10211160 | Microelectronic assembly with redistribution structure formed on carrier | Wael Zohni, Cyprian Emeka Uzoh | 2019-02-19 |
| 10159148 | Porous alumina templates for electronic packages | Rajesh Katkar, Cyprian Emeka Uzoh, Ilyas Mohammed | 2018-12-18 |
| 10157978 | High density three-dimensional integrated capacitors | Vage Oganesian, Ilyas Mohammed, Piyush Savalia | 2018-12-18 |
| 10149377 | Stacked transmission line | Shaowu Huang, Javier A. Delacruz | 2018-12-04 |