Issued Patents All Time
Showing 26–50 of 60 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6841460 | Anti-type dosage as LDD implant | Shu-Ying Cho, Chien-Chung Wang, Chien-Ming Chung | 2005-01-11 |
| 6734085 | Anti-type dosage as LDD implant | Shu-Ying Cho, Chien-Chung Wang, Chien-Ming Chung | 2004-05-11 |
| 6727155 | Method for spin etching sidewall spacers by acid vapor | Jiunn-Der Yang, Chaucer Chnug | 2004-04-27 |
| 6656772 | Method for bonding inner leads to bond pads without bumps and structures formed | — | 2003-12-02 |
| 6501525 | Method for interconnecting a flat panel display having a non-transparent substrate and devices formed | Tai-Hong Chen | 2002-12-31 |
| 6242312 | Advanced titanium silicide process for very narrow polysilicon lines | Ding Hu, Hong-Che Hsiue, Chao-Ray Wang | 2001-06-05 |
| 6242350 | Post gate etch cleaning process for self-aligned gate mosfets | Hun-Jan Tao, Chia-Shiung Tsai | 2001-06-05 |
| 6211083 | Use of a novel capped anneal procedure to improve salicide formation | Jiunn-Der Yang, Chaucer Chung | 2001-04-03 |
| 6184149 | Method for monitoring self-aligned contact etching | Li-Chih Chao | 2001-02-06 |
| 6172411 | Self-aligned contact structures using high selectivity etching | Li-Chih Chao, Jhon Jhy Liaw, Jin-Yuan Lee | 2001-01-09 |
| 6156629 | Method for patterning a polysilicon gate in deep submicron technology | Hun-Jan Tao | 2000-12-05 |
| 6077778 | Method of improving refresh time in DRAM products | Yung Kuan Hsiao, Min-Hsiung Chiang | 2000-06-20 |
| 6030879 | Method of reducing particles during the manufacturing of fin or cylinder capacitors on a wafer | Yung Kuan Hsiao, Dah Jong Ou Yang | 2000-02-29 |
| 5981385 | Dimple elimination in a tungsten etch back process by reverse image patterning | — | 1999-11-09 |
| 5943569 | Method for making improved capacitors on dynamic random access memory having increased capacitance, longer refresh times, and improved yields | Cheng-Yeh Shih, Chue-San Yoo, Wen Chan Lin | 1999-08-24 |
| 5900644 | Test site and a method of monitoring via etch depths for semiconductor devices | Shu-Lan Ying, Jue-Jye Chen, Yuh-Jier Mii | 1999-05-04 |
| 5895257 | LOCOS field oxide and field oxide process using silicon nitride spacers | Chaochieh Tsai, Juing-Yi Wu, Shun-Liang Hsu | 1999-04-20 |
| 5872063 | Self-aligned contact structures using high selectivity etching | Li-Chih Chao, Jhon Jhy Liaw, Jin-Yuan Lee | 1999-02-16 |
| 5837428 | Etching method for extending i-line photolithography to 0.25 micron linewidth | Shu-Chih Yang | 1998-11-17 |
| 5792705 | Optimized planarization process for SOG filled vias | Chin-Kun Wang, Iman Hsu | 1998-08-11 |
| 5753418 | 0.3 Micron aperture width patterning process | Chia-Shiung Tsai, Chen-Hua Yu | 1998-05-19 |
| 5747379 | Method of fabricating seamless tungsten plug employing tungsten redeposition and etch back | Kuan-Hui Chang | 1998-05-05 |
| 5702956 | Test site and a method of monitoring via etch depths for semiconductor devices | Shu-Lan Ying, Jue-Jye Chen, Yuh-Jier Mii | 1997-12-30 |
| 5679211 | Spin-on-glass etchback planarization process using an oxygen plasma to remove an etchback polymer residue | — | 1997-10-21 |
| 5672914 | Dimple-free tungsten plug | Huang-Hui Chang | 1997-09-30 |