Issued Patents All Time
Showing 1–20 of 20 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7253112 | Dual damascene process | Bang-Chien Ho, Jian-Hong Chen, Tsang-Jiuh Wu, Li-Te Lin, Hua-Tai Lin +1 more | 2007-08-07 |
| 6797630 | Partial via hard mask open on low-k dual damascene etch with dual hard mask (DHM) approach | Tsang-Jiuh Wu, Chen-Nan Yeh, Li-Te Lin | 2004-09-28 |
| 6743732 | Organic low K dielectric etch with NH3 chemistry | Li-Te Lin, Chia-Shiung Tsai | 2004-06-01 |
| 6727183 | Prevention of spiking in ultra low dielectric constant material | Ching-Hui Ma, Jen-Cheng Liu | 2004-04-27 |
| 6720256 | Method of dual damascene patterning | Tsang-Jiuh Wu, Li-Te Lin | 2004-04-13 |
| 6551938 | N2/H2 chemistry for dry development in top surface imaging technology | Tsang-Jiuh Wu, Li-Te Lin | 2003-04-22 |
| 6495469 | High selectivity, low etch depth micro-loading process for non stop layer damascene etch | Jiing-Feng Yang, Li-Te Lin | 2002-12-17 |
| 6458650 | CU second electrode process with in situ ashing and oxidation process | Yi-Chen Huang, Chao-Chen Chen | 2002-10-01 |
| 6457477 | Method of cleaning a copper/porous low-k dual damascene etch | Bao-Ru Young, Shwangming Jeng, Chi-Shiung Tsai | 2002-10-01 |
| 6429119 | Dual damascene process to reduce etch barrier thickness | Chia-Shiung Tsai, Ming-Huei Lui, Jen-Cheng Liu, Chao-Cheng Chen | 2002-08-06 |
| 6376366 | Partial hard mask open process for hard mask dual damascene etch | Li-Te Lin | 2002-04-23 |
| 6323121 | Fully dry post-via-etch cleaning method for a damascene process | Jen-Cheng Liu, Chao-Cheng Chen, Chia-Shiung Tsai, Ming-Huei Lui | 2001-11-27 |
| 6211061 | Dual damascene process for carbon-based low-K materials | Chao-Cheng Chen, Ming-Huei Lui, Jen-Cheng Liu, Chia-Shiung Tsai | 2001-04-03 |
| 6184149 | Method for monitoring self-aligned contact etching | Yuan-Chang Huang | 2001-02-06 |
| 6172411 | Self-aligned contact structures using high selectivity etching | Jhon Jhy Liaw, Yuan-Chang Huang, Jin-Yuan Lee | 2001-01-09 |
| 6165880 | Double spacer technology for making self-aligned contacts (SAC) on semiconductor integrated circuits | Dun-Nian Yaung, Shou-Gwo Wuu, Kuo-Ching Huang | 2000-12-26 |
| 6140218 | Method for fabricating a T-shaped hard mask/conductor profile to improve self-aligned contact isolation | Jen-Cheng Liu, Huan-Just Lin, Yung Kuan Hsiao | 2000-10-31 |
| 6107206 | Method for etching shallow trenches in a semiconductor body | Chao-Cheng Chen | 2000-08-22 |
| 6063711 | High selectivity etching stop layer for damascene process | Chia-Shiung Tsai, Chu-Yun Fu, Jhon Jhy Liaw | 2000-05-16 |
| 5872063 | Self-aligned contact structures using high selectivity etching | Jhon Jhy Liaw, Yuan-Chang Huang, Jin-Yuan Lee | 1999-02-16 |