Issued Patents All Time
Showing 101–125 of 303 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11282742 | Semiconductor device with multi-layer etch stop structure and method for forming the same | Po-Cheng Shih, Jen Hung Wang, Yu-Kai Lin, Su-Jen Sung | 2022-03-22 |
| 11282712 | Method for preventing bottom layer wrinkling in a semiconductor device | Jung-Hau Shiu, Chung-Chi Ko, Yu-Yun Peng | 2022-03-22 |
| 11271083 | Semiconductor device, FinFET device and methods of forming the same | Po-Hsien Cheng, Jr-Hung Li, Tai-Chun Huang, Chung-Ting Ko, Jr-Yu Chen +1 more | 2022-03-08 |
| 11257951 | Method of making semiconductor device having first and second epitaxial materials | Lilly Su, Chii-Horng Li, Ming-Hua Yu, Pang-Yen Tsai, Yen-Ru Lee | 2022-02-22 |
| 11244822 | Apparatus for manufacturing a thin film and a method therefor | Tsai-Fu Hsiao, Kuang-Yuan Hsu, Pei-Ren Jeng | 2022-02-08 |
| 11239310 | Seamless gap fill | Yen-Chun Huang, Bor Chiuan Hsieh, Pei-Ren Jeng, Tai-Chun Huang | 2022-02-01 |
| 11164789 | Method for forming semiconductor device that includes covering metal gate with multilayer dielectric | Tsai-Jung Ho, Yu-Shih Wang | 2021-11-02 |
| 11164948 | Field-effect transistor and method of manufacturing the same | Tsai-Jung Ho, Jr-Hung Li, Pei-Yu Chou, Chi-Ta Lee | 2021-11-02 |
| 11107921 | Source/drain recess in a semiconductor device | Eric Peng, Chao-Cheng Chen, Chii-Horng Li, Ming-Hua Yu, Shih-Hao Lo +2 more | 2021-08-31 |
| 11107902 | Dielectric spacer to prevent contacting shorting | Ting-Gang Chen, Tai-Chun Huang, Yi-Ting Fu, Ming-Chang Wen, Shu-Yuan Ku +2 more | 2021-08-31 |
| 11069528 | Semiconductor device and method | Ching-Yu Chang, Jung-Hau Shiu, Jen Hung Wang | 2021-07-20 |
| 11053584 | System and method for supplying a precursor for an atomic layer deposition (ALD) process | Bor Chiuan Hsieh, Chien-Kuo Huang, Tai-Chun Huang, Kuang-Yuan Hsu | 2021-07-06 |
| 11049763 | Multi-patterning to form vias with straight profiles | Chun-Kai Chen, Jung-Hau Shiu, Chia-Cheng Chou, Chung-Chi Ko, Chih-Hao Chen +1 more | 2021-06-29 |
| 11008654 | Apparatus and method for spatial atomic layer deposition | Anthony Hong Lin, Ching-Lun Lai, Pei-Ren Jeng | 2021-05-18 |
| 10978301 | Morphology of resist mask prior to etching | Ching-Yu Chang, Jung-Hau Shiu, Wei-Ren Wang, Shing-Chyang Pan | 2021-04-13 |
| 10916656 | MOS devices having epitaxy regions with reduced facets | Hsueh-Chang Sung, Kun-Mu Li, Chii-Horng Li, Tsz-Mei Kwok | 2021-02-09 |
| 10867807 | Semiconductor device and method | Ming-Jie Huang, Syun-Ming Jang, Ryan Chia-Jen Chen, Ming-Ching Chang, Shu-Yuan Ku +3 more | 2020-12-15 |
| 10867839 | Patterning methods for semiconductor devices | Wei-Ren Wang, Shing-Chyang Pan, Ching-Yu Chang, Wan-Lin Tsai, Jung-Hau Shiu | 2020-12-15 |
| 10867794 | Patterning method for semiconductor devices and structures resulting therefrom | Ching-Yu Chang, Jung-Hau Shiu, Szu-Ping Tung, Chun-Kai Chen, Jen Hung Wang | 2020-12-15 |
| 10861971 | Doping profile for strained source/drain region | Hsueh-Chang Sung, Tsz-Mei Kwok, Kun-Mu Li, Chii-Horng Li | 2020-12-08 |
| 10861975 | FinFET with rounded source/drain profile | Ming-Hua Yu, Chih-Pin Tsao, Pei-Ren Jeng | 2020-12-08 |
| 10854748 | Semiconductor device having first and second epitaxial materials | Lilly Su, Pang-Yen Tsai, Chii-Horng Li, Yen-Ru Lee, Ming-Hua Yu | 2020-12-01 |
| 10854729 | Method to reduce etch variation using ion implantation | Tsan-Chun Wang, Ziwei Fang, Chii-Horng Li, Chao-Cheng Chen, Syun-Ming Jang | 2020-12-01 |
| 10840134 | Interconnect structure and method | Chia-Cheng Chou, Chih-Chien Chi, Chung-Chi Ko, Yao-Jen Chang, Chen-Yuan Kao +3 more | 2020-11-17 |
| 10811537 | Semiconductor device having fins | Che-Yu Lin, Ming-Hua Yu, Chan-Lon Yang | 2020-10-20 |