Issued Patents All Time
Showing 76–98 of 98 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8803316 | TSV structures and methods for forming the same | Yung-Chi Lin, Hsin-Yu Chen, Wen-Chih Chiou, Ku-Feng Yang, Jing-Cheng Lin | 2014-08-12 |
| 8803322 | Through substrate via structures and methods of forming the same | Ku-Feng Yang, Yi-Hsiu Chen, Ebin Liao, Yuan-Hung Liu, Wen-Chih Chiou | 2014-08-12 |
| 8673775 | Methods of forming semiconductor structures | Wen-Chih Chiou, Ku-Feng Yang, Hsin-Yu Chen | 2014-03-18 |
| 8674513 | Interconnect structures for substrate | Chen-Hua Yu, Wen-Chih Chiou, Shin-Puu Jeng | 2014-03-18 |
| 8587127 | Semiconductor structures and methods of forming the same | Wen-Chih Chiou, Ku-Feng Yang, Hsin-Yu Chen | 2013-11-19 |
| 8580682 | Cost-effective TSV formation | Ku-Feng Yang, Yung-Chi Lin, Hung-Pin Chang, Wen-Chih Chiou | 2013-11-12 |
| 8575725 | Through-silicon vias for semicondcutor substrate and method of manufacture | Chen-Hua Yu, Cheng-Hung Chang, Ebin Liao, Chia-Lin Yu, Hsiang-Yi Wang +4 more | 2013-11-05 |
| 8531035 | Interconnect barrier structure and method | Chen-Hua Yu, Wen-Chih Chiou | 2013-09-10 |
| 8525343 | Device with through-silicon via (TSV) and method of forming the same | Chen-Hua Yu, Wen-Chih Chiou, Ebin Liao | 2013-09-03 |
| 8487410 | Through-silicon vias for semicondcutor substrate and method of manufacture | Chen-Hua Yu, Cheng-Hung Chang, Ebin Liao, Chia-Lin Yu, Hsiang-Yi Wang +4 more | 2013-07-16 |
| 8466059 | Multi-layer interconnect structure for stacked dies | Hung-Pin Chang, Chien-Ming Chiu, Shau-Lin Shue, Chen-Hua Yu | 2013-06-18 |
| 8445296 | Apparatus and methods for end point determination in reactive ion etching | Chien Rhone Wang, Tzu-Cheng Lin, Yu-Jen Cheng, Chih-Wei Lai, Hung-Pin Chang | 2013-05-21 |
| 7670947 | Metal interconnect structure and process for forming same | Syun-Ming Jang, Ming-Chung Liang, Hsin-Yi Tsai | 2010-03-02 |
| 7629690 | Dual damascene process without an etch stop layer | Syun-Ming Jang | 2009-12-08 |
| 7414315 | Damascene structure with high moisture-resistant oxide and method for making the same | Syun-Ming Jang | 2008-08-19 |
| 7265060 | Bi-level resist structure and fabrication method for contact holes on semiconductor substrates | Ming-Huan Tsai, Hun-Jan Tao, Ju-Wang Hsu | 2007-09-04 |
| 7253112 | Dual damascene process | Bang-Chien Ho, Jian-Hong Chen, Li-Te Lin, Li-Chih Chao, Hua-Tai Lin +1 more | 2007-08-07 |
| 6914007 | In-situ discharge to avoid arcing during plasma etch processes | Ching-Hui Ma, Chao-Cheng Chen, Hui Yu, Hun-Jan Tao | 2005-07-05 |
| 6797630 | Partial via hard mask open on low-k dual damascene etch with dual hard mask (DHM) approach | Chen-Nan Yeh, Li-Te Lin, Li-Chih Chao | 2004-09-28 |
| 6780782 | Bi-level resist structure and fabrication method for contact holes on semiconductor substrates | Ming-Huan Tsai, Hun-Jan Tao, Ju-Wang Hsu | 2004-08-24 |
| 6720256 | Method of dual damascene patterning | Li-Te Lin, Li-Chih Chao | 2004-04-13 |
| 6551938 | N2/H2 chemistry for dry development in top surface imaging technology | Li-Te Lin, Li-Chih Chao | 2003-04-22 |
| 6246175 | Large area microwave plasma generator | Chwung-Shan Kou | 2001-06-12 |