Issued Patents All Time
Showing 51–75 of 253 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10714620 | FinFETs and methods of forming FinFETs | Chin-Hsiang Lin, Tai-Chun Huang | 2020-07-14 |
| 10700000 | Semiconductor structure and method making the same | Hsin-Yen Huang, Kai-Fang Cheng, Chi-Lin Teng, Hai-Ching Chen | 2020-06-30 |
| 10679846 | System and method of forming a porous low-K structure | Bo-Jiun Lin, Hai-Ching Chen | 2020-06-09 |
| 10665467 | Spacer etching process for integrated circuit design | Ru-Gun Liu, Cheng-Hsiung Tsai, Chung-Ju Lee, Chih-Ming Lai, Chia-Ying Lee +6 more | 2020-05-26 |
| 10629479 | Structure and method for interconnection | Chih Wei Lu, Chung-Ju Lee | 2020-04-21 |
| 10539751 | Optical bench on substrate | Wan-Yu Lee, Chun-Hao Tseng, Hai-Ching Chen | 2020-01-21 |
| 10527788 | Package structure and methods of forming same | Jui Hsieh Lai, Ying-Hao Kuo, Hai-Ching Chen | 2020-01-07 |
| 10515823 | Via connection to a partially filled trench | Shih-Ming Chang, Chih-Ming Lai, Ru-Gun Liu, Tsai-Sheng Gau, Chung-Ju Lee +1 more | 2019-12-24 |
| 10505018 | Spacers with rectangular profile and methods of forming the same | Yu-Sheng Chang, Chung-Ju Lee | 2019-12-10 |
| 10490650 | Low-k gate spacer and methods for forming the same | Wen-Kai Lin, Bo-Yu Lai, Li Chun Te, Kai-Hsuan Lee, Sai-Hooi Yeong +1 more | 2019-11-26 |
| 10483169 | FinFET cut-last process using oxide trench fill | Yen-Chun Huang, Chih-Tang Peng, Kuang-Yuan Hsu, Tai-Chun Huang, Tsu-Hsiu Perng | 2019-11-19 |
| 10408998 | Method of fabrication polymer waveguide | Chun-Hao Tseng, Wan-Yu Lee, Hai-Ching Chen | 2019-09-10 |
| 10353147 | Etchant and etching process for substrate of a semiconductor device | Wan-Yu Lee, Ying-Hao Kuo, Hai-Ching Chen | 2019-07-16 |
| 10354954 | Copper etching integration scheme | Chih Wei Lu, Chung-Ju Lee, Hsiang-Huan Lee | 2019-07-16 |
| 10332838 | Schemes for forming barrier layers for copper in interconnect structures | Chen-Hua Yu, Hai-Ching Chen | 2019-06-25 |
| 10312136 | Etch damage and ESL free dual damascene metal interconnect | Sunil Kumar Singh, Chung-Ju Lee | 2019-06-04 |
| 10312139 | Interconnect structure having an etch stop layer over conductive lines | Cheng-Hsiung Tsai, Chung-Ju Lee, Shau-Lin Shue | 2019-06-04 |
| 10290536 | Structure and method for interconnection | Chih Wei Lu, Chung-Ju Lee | 2019-05-14 |
| 10269757 | Integrated circuit with a thermally conductive underfill and methods of forming same | Chen-Hua Yu | 2019-04-23 |
| 10269634 | Semiconductor device having voids and method of forming same | Yung-Hsu Wu, Chien-Hua Huang, Chung-Ju Lee, Shau-Lin Shue | 2019-04-23 |
| 10269567 | Multi-layer mask and method of forming same | Teng-Chun Tsai, Yung-Cheng Lu, Ying-Tsung Chen | 2019-04-23 |
| 10261248 | Package structure and methods of forming same | Jui Hsieh Lai, Ying-Hao Kuo, Hai-Ching Chen | 2019-04-16 |
| 10180547 | Optical bench on substrate | Wan-Yu Lee, Chun-Hao Tseng, Hai-Ching Chen | 2019-01-15 |
| 10170306 | Method of double patterning lithography process using plurality of mandrels for integrated circuit applications | Chung-Ju Lee, Hsin-Chieh Yao, Shau-Lin Shue, Yung-Hsu Wu | 2019-01-01 |
| 10163797 | Forming interlayer dielectric material by spin-on metal oxide deposition | Chi-Lin Teng, Jung-Hsun Tsai, Kai-Fang Cheng, Hsin-Yen Huang, Hai-Ching Chen | 2018-12-25 |