Issued Patents All Time
Showing 26–49 of 49 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9318606 | FinFET device and method of fabricating same | Chih-Hao Wang, Kuo-Cheng Ching, Zhiqiang Wu | 2016-04-19 |
| 9202917 | Buried SiGe oxide FinFET scheme for device enhancement | Kuo-Cheng Ching, Chih-Hao Wang, Zhiqiang Wu | 2015-12-01 |
| 9153670 | Semiconductor device and fabricating the same | Chih-Hao Wang, Kuo-Cheng Ching, Zhiqiang Wu | 2015-10-06 |
| 9006842 | Tuning strain in semiconductor devices | Jean-Pierre Colinge, Kuo-Cheng Ching, Zhiqiang Wu, Chih-Hao Wang, Carlos H. Diaz | 2015-04-14 |
| 8943445 | Method of merging color sets of layout | Pi-Tsung Chen, Ming-Hui Chih, Ken-Hsien Hsieh, Wei-Long Wang, Wen-Chun Huang +4 more | 2015-01-27 |
| 8907441 | Methods for double-patterning-compliant standard cell design | Huang-Yu Chen, Yuan-Te Hou, Fung Song Lee, Wen-Ju Yang, Yi-Kan Cheng +2 more | 2014-12-09 |
| 8901607 | Semiconductor device and fabricating the same | Chih-Hao Wang, Kuo-Cheng Ching, Zhiqiang Wu | 2014-12-02 |
| 8826207 | Method of generating technology file for integrated circuit design tools | Cliff Hou, Cheng-Hung Yeh, Chih-Tsung Yao | 2014-09-02 |
| 8633516 | Source/drain stack stressor for semiconductor device | Zhiqiang Wu, Kuo-Cheng Ching, Chun Chung Su, Shi Ning Ju | 2014-01-21 |
| 8631379 | Decomposing integrated circuit layout | Pi-Tsung Chen, Ming-Hui Chih, Ken-Hsien Hsieh, Wei-Long Wang, Wen-Chun Huang +4 more | 2014-01-14 |
| 8572537 | Accurate parasitic capacitance extraction for ultra large scale integrated circuits | Ke-Ying Su, Chia-Ming Ho, Chien-Wen Chen | 2013-10-29 |
| 8336002 | IC design flow enhancement with CMP simulation | Yi-Kan Cheng, Ivy Chiu, Ke-Ying Su | 2012-12-18 |
| 8286114 | 3-dimensional device design layout | Harry-Hak-Lay Chuang, Kong-Beng Thei, Mong-Song Liang, Sheng-Chen Chung, Chih-Tsung Yao +3 more | 2012-10-09 |
| 8239806 | Routing system and method for double patterning technology | Huang-Yu Chen, Yuan-Te Hou, Wen-Ju Yang, Zhe-Wei Jiang, Yi-Kan Cheng +1 more | 2012-08-07 |
| 8227869 | Performance-aware logic operations for generating masks | Lee-Chung Lu, Chung-Te Lin, Yen-Sen Wang, Yao-Jen Chuang | 2012-07-24 |
| 8214784 | Accurate parasitic capacitance extraction for ultra large scale integrated circuits | Ke-Ying Su, Chia-Ming Ho, Chien-Wen Chen | 2012-07-03 |
| 8136168 | System and method for design-for-manufacturability data encryption | Yi-Kan Cheng, Jill Liu, Hsiao-Shu Chiao | 2012-03-13 |
| 8122394 | Performance-aware logic operations for generating masks | Lee-Chung Lu, Chung-Te Lin, Yen-Sen Wang, Yao-Jen Chuang | 2012-02-21 |
| 7966596 | Place-and-route layout method with same footprint cells | Lee-Chung Lu, Chung-Hsing Wang, Ping Li, Chun-Hui Tai, Li-Chun Tien | 2011-06-21 |
| 7904844 | System, method, and computer program product for matching cell layout of an integrated circuit design | Cheng-Hung Yeh, Feng-Ming Chang, Ping-Wei Wang | 2011-03-08 |
| 7818698 | Accurate parasitic capacitance extraction for ultra large scale integrated circuits | Ke-Ying Su, Chia-Ming Ho, Chien-Wen Chen | 2010-10-19 |
| 7801717 | Method for smart dummy insertion to reduce run time and dummy count | Yi-Kan Cheng, Cliff Hou | 2010-09-21 |
| 7797668 | Method for optimally converting a circuit design into a semiconductor device | Ru-Gun Liu, Chih-Ming Lai, Yung-Chin Hou | 2010-09-14 |
| 7788612 | System, method, and computer program product for matching cell layout of an integrated circuit design | Cheng-Hung Yeh, Feng-Ming Chang, Ping-Wei Wang | 2010-08-31 |