Issued Patents All Time
Showing 76–100 of 109 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8847389 | Method and apparatus for a conductive bump structure | Jung-Hua Chang, Jing-Cheng Lin | 2014-09-30 |
| 8803337 | Integrated circuit structure having dies with connectors | Jing-Cheng Lin | 2014-08-12 |
| 8779599 | Packages including active dies and dummy dies and methods for forming the same | Jing-Cheng Lin, Szu-Wei Lu, Jui-Pin Hung, Shin-Puu Jeng, Chen-Hua Yu | 2014-07-15 |
| 8759118 | Plating process and structure | Chin-Fu Kao, Jing-Cheng Lin | 2014-06-24 |
| 8698308 | Bump structural designs to minimize package defects | Jing-Cheng Lin | 2014-04-15 |
| 8664760 | Connector design for packaging integrated circuits | Chen-Hua Yu, Shin-Puu Jeng, Shang-Yun Hou, Cheng-Chieh Hsieh, Kuo-Ching Hsu +4 more | 2014-03-04 |
| 8653664 | Barrier layers for copper interconnect | Nai-Wei Liu, Zhen-Cheng Wu, Po-Hsiang Huang, Yung-Chih Wang, Shu-Hui Su +2 more | 2014-02-18 |
| 8629058 | Methods for via structure with improved reliability | Shau-Lin Shue, Ching-Hua Hsieh | 2014-01-14 |
| 8610285 | 3D IC packaging structures and methods with a metal pillar | Chen-Hua Yu, Shin-Puu Jeng, Shang-Yun Hou, Kuo-Ching Hsu, Cheng-Chieh Hsieh +3 more | 2013-12-17 |
| 8536573 | Plating process and structure | Chin-Fu Kao, Jing-Cheng Lin | 2013-09-17 |
| 8456009 | Semiconductor structure having an air-gap region and a method of manufacturing the same | Shu-Hui Su, Jiing-Feng Yang, Zhen-Cheng Wu, Ren-Guei Wu, Dian-Hau Chen +1 more | 2013-06-04 |
| 8426307 | Reducing resistivity in interconnect structures of integrated circuits | — | 2013-04-23 |
| 8304906 | Partial air gap formation for providing interconnect isolation in integrated circuits | Jiing-Feng Yang, Chii-Ping Chen, Dian-Hau Chen, Yuh-Jier Mii | 2012-11-06 |
| 8264086 | Via structure with improved reliability | Shau-Lin Shue, Ching-Hua Hsieh | 2012-09-11 |
| 8252690 | In situ Cu seed layer formation for improving sidewall coverage | Li-Lin Su, Shing-Chyang Pan, Ching-Hua Hsieh | 2012-08-28 |
| 8034709 | Method for forming composite barrier layer | Ching-Hua Hsieh, Hsien-Ming Lee, Shing-Chyang Pan, Chao-Hsien Peng, Li-Lin Su +3 more | 2011-10-11 |
| 7956465 | Reducing resistivity in interconnect structures of integrated circuits | — | 2011-06-07 |
| 7919862 | Reducing resistivity in interconnect structures of integrated circuits | — | 2011-04-05 |
| 7704886 | Multi-step Cu seed layer formation for improving sidewall coverage | Li-Lin Su, Shing-Chyang Pan, Ching-Hua Hsieh | 2010-04-27 |
| 7700479 | Cleaning processes in the formation of integrated circuit interconnect structures | Ching-Hua Hsieh, Shau-Lin Shue | 2010-04-20 |
| 7612451 | Reducing resistivity in interconnect structures by forming an inter-layer | Chih-Chao Shih, Ching-Hua Hsieh, Shau-Lin Shue | 2009-11-03 |
| 7453149 | Composite barrier layer | Ching-Hua Hsieh, Hsien-Ming Lee, Shing-Chyang Pan, Chao-Hsien Peng, Li-Lin Su +3 more | 2008-11-18 |
| 7338909 | Micro-etching method to replicate alignment marks for semiconductor wafer photolithography | Yu-Liang Lin, Henry Lo, Chung-Long Chang, Gorge Huang, Tony Lu +8 more | 2008-03-04 |
| 7253501 | High performance metallization cap layer | Hsien-Ming Lee, Jing-Cheng Lin, Shing-Chyang Pan, Ching-Hua Hsieh, Chao-Hsien Peng +2 more | 2007-08-07 |
| 7215024 | Barrier-less integration with copper alloy | Jing-Cheng Lin, Ching-Hua Hsieh, Shau-Lin Shue, Mong-Song Liang | 2007-05-08 |