Issued Patents All Time
Showing 51–75 of 108 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9754958 | Three-dimensional memory devices having a shaped epitaxial channel portion and method of making thereof | Sateesh Koka, Raghuveer S. Makala, Somesh Peri | 2017-09-05 |
| 9748267 | Three dimensional NAND device with channel contacting conductive source line and method of making thereof | Yanli Zhang, Go Shoji, Johann Alsmeier, Yingda Dong, Jiahui Yuan | 2017-08-29 |
| 9698152 | Three-dimensional memory structure with multi-component contact via structure and method of making thereof | Somesh Peri, Sateesh Koka, Raghuveer S. Makala, Rahul Sharangpani, Matthias Baenninger +1 more | 2017-07-04 |
| 9685454 | Method of forming 3D vertical NAND with III-V channel | Peter Rabkin, Johann Alsmeier, Masaaki Higashitani | 2017-06-20 |
| 9666590 | High stack 3D memory and method of making | Henry Chien, Johann Alsmeier | 2017-05-30 |
| 9666593 | Alternating refractive index in charge-trapping film in three-dimensional memory | Liang Pang, Yingda Dong | 2017-05-30 |
| 9666594 | Multi-charge region memory cells for a vertical NAND device | Genta Mizuno, Masanori Tsutsumi | 2017-05-30 |
| 9659956 | Three-dimensional memory device containing source select gate electrodes with enhanced electrical isolation | Tuan Pham, Henry Chien | 2017-05-23 |
| 9627403 | Multilevel memory stack structure employing support pillar structures | Jin Liu, Tong Zhang, Yao-Sheng Lee, Johann Alsmeier | 2017-04-18 |
| 9583500 | Multilevel memory stack structure and methods of manufacturing the same | Johann Alsmeier, Henry Chien | 2017-02-28 |
| 9564219 | Current based detection and recording of memory hole-interconnect spacing defects | Sagar Magia, Jagdish Sabde, Ankitkumar Babariya | 2017-02-07 |
| 9559117 | Three-dimensional non-volatile memory device having a silicide source line and method of making thereof | Yingda Dong, Johann Alsmeier | 2017-01-31 |
| 9543320 | Three-dimensional memory structure having self-aligned drain regions and methods of making thereof | Liang Pang, Yingda Dong | 2017-01-10 |
| 9530514 | Select gate defect detection | Jagdish Sabde, Sagar Magia | 2016-12-27 |
| 9524981 | Three dimensional memory device with hybrid source electrode for wafer warpage reduction | Johann Alsmeier | 2016-12-20 |
| 9524976 | Method of integrating select gate source and memory hole for three-dimensional non-volatile memory device | Johann Alsmeier, Henry Chien | 2016-12-20 |
| 9520406 | Method of making a vertical NAND device using sequential etching of multilayer stacks | Raghuveer S. Makala, Yao-Sheng Lee, Johann Alsmeier, Henry Chien | 2016-12-13 |
| 9515085 | Vertical memory device with bit line air gap | Peter Rabkin, Jilin Xia | 2016-12-06 |
| 9496274 | Three-dimensional non-volatile memory device | Johann Alsmeier, Raghuveer S. Makala, Yao-Sheng Lee | 2016-11-15 |
| 9478495 | Three dimensional memory device containing aluminum source contact via structure and method of making thereof | Peter Rabkin, Jilin Xia, Christopher J. Petti | 2016-10-25 |
| 9460931 | High aspect ratio memory hole channel contact formation | Johann Alsmeier, Raghuveer S. Makala, Yao-Sheng Lee | 2016-10-04 |
| 9455263 | Three dimensional NAND device with channel contacting conductive source line and method of making thereof | Yanli Zhang, Go Shoji, Johann Alsmeier, Yingda Dong, Jiahui Yuan | 2016-09-27 |
| 9449982 | Method of making a vertical NAND device using a sacrificial layer with air gap and sequential etching of multilayer stacks | Zhenyu Lu, Sateesh Koka, James Kai, Raghuveer S. Makala, Yao-Sheng Lee +2 more | 2016-09-20 |
| 9449985 | Memory cell with high-k charge trapping layer | Peter Rabkin, Johann Alsmeier, Masaaki Higashitani | 2016-09-20 |
| 9449981 | Three dimensional NAND string memory devices and methods of fabrication thereof | Johann Alsmeier, Henry Chien | 2016-09-20 |