Issued Patents All Time
Showing 26–50 of 108 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10381434 | Support pillar structures for leakage reduction in a three-dimensional memory device | Hiroyuki Kinoshita, Yao-Sheng Lee | 2019-08-13 |
| 10128257 | Select transistors with tight threshold voltage in 3D memory | Liang Pang, Yingda Dong | 2018-11-13 |
| 10121794 | Three-dimensional memory device having epitaxial germanium-containing vertical channel and method of making thereof | Marika Gunji-Yoneoka, Atsushi Suyama, Tsuyoshi Hada, Daewung Kang, Murshed Chowdhury +4 more | 2018-11-06 |
| 10115459 | Multiple liner interconnects for three dimensional memory devices and method of making thereof | Katsuo Yamada, Tomoyasu Kakegawa, Peter Rabkin, Mohan Dunga, Masaaki Higashitani | 2018-10-30 |
| 10103161 | Offset backside contact via structures for a three-dimensional memory device | Fumitoshi Ito, Masaaki Higashitani, Cheng-Chung Chu, Tuan Pham | 2018-10-16 |
| 10032524 | Techniques for determining local interconnect defects | Jagdish Sabde, Sagar Magia | 2018-07-24 |
| 10014316 | Three-dimensional memory device with leakage reducing support pillar structures and method of making thereof | Fabo Yu, Jongsun Sel, Tuan Pham, Cheng-Chung Chu, Yao-Sheng Lee +3 more | 2018-07-03 |
| 9953717 | NAND structure with tier select gate transistors | Jagdish Sabde, Peter Rabkin | 2018-04-24 |
| 9941295 | Method of making a three-dimensional memory device having a heterostructure quantum well channel | Peter Rabkin, Johann Alsmeier, Masaaki Higashitani | 2018-04-10 |
| 9941293 | Select transistors with tight threshold voltage in 3D memory | Liang Pang, Yingda Dong | 2018-04-10 |
| 9934872 | Erase stress and delta erase loop count methods for various fail modes in non-volatile memory | Sagar Magia, Jagdish Sabde | 2018-04-03 |
| 9917093 | Inter-plane offset in backside contact via structures for a three-dimensional memory device | Cheng-Chung Chu, Tuan Pham, Fumitoshi Ito, Masaaki Higashitani | 2018-03-13 |
| 9881929 | Multi-tier memory stack structure containing non-overlapping support pillar structures and method of making thereof | Pradhyumna Ravikirthi, Jagdish Sabde, Peter Rabkin | 2018-01-30 |
| 9876025 | Methods for manufacturing ultrathin semiconductor channel three-dimensional memory devices | Peter Rabkin, Masaaki Higashitani, Johann Alsmeier | 2018-01-23 |
| 9870945 | Crystalline layer stack for forming conductive layers in a three-dimensional memory structure | Matthias Baenninger, Stephen Shi, Johann Alsmeier, Henry Chien | 2018-01-16 |
| 9859298 | Amorphous silicon layer in memory device which reduces neighboring word line interference | Liang Pang, Yingda Dong | 2018-01-02 |
| 9842851 | Three-dimensional memory devices having a shaped epitaxial channel portion | Tuan Pham | 2017-12-12 |
| 9831118 | Reducing neighboring word line in interference using low-k oxide | Liang Pang, Yingda Dong, Ching-Huang Lu | 2017-11-28 |
| 9830998 | Stress patterns to detect shorts in three dimensional non-volatile memory | Sagar Magia, Ankitkumar Babariya, Jagdish Sabde | 2017-11-28 |
| 9825051 | Three dimensional NAND device containing fluorine doped layer and method of making thereof | Peter Rabkin, Johann Alsmeier | 2017-11-21 |
| 9799669 | Single-semiconductor-layer channel in a memory opening for a three-dimensional non-volatile memory device | Peter Rabkin, Johann Alsmeier | 2017-10-24 |
| 9799671 | Three-dimensional integration schemes for reducing fluorine-induced electrical shorts | Matthias Baenninger, Stephen Shi, Johann Alsmeier | 2017-10-24 |
| 9793283 | High conductivity channel for 3D memory | Liang Pang, Yingda Dong | 2017-10-17 |
| 9780108 | Ultrathin semiconductor channel three-dimensional memory devices | Peter Rabkin, Masaaki Higashitani, Johann Alsmeier | 2017-10-03 |
| 9761604 | 3D vertical NAND with III-V channel | Peter Rabkin, Johann Alsmeier, Masaaki Higashitani | 2017-09-12 |