Issued Patents All Time
Showing 51–75 of 94 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10541035 | Read bias adjustment for compensating threshold voltage shift due to lateral charge movement | Han-Ping Chen, Chung-Yao Pai, Yingda Dong | 2020-01-21 |
| 10510413 | Multi-pass programming with modified pass voltages to tighten threshold voltage distributions | Vinh Diep | 2019-12-17 |
| 10482981 | Preventing refresh of voltages of dummy memory cells to reduce threshold voltage downshift for select gate transistors | Vinh Diep | 2019-11-19 |
| 10446244 | Adjusting voltage on adjacent word line during verify of memory cells on selected word line in multi-pass programming | Vinh Diep, Zhengyi Zhang, Yingda Dong | 2019-10-15 |
| 10373697 | Programming dummy memory cells in erase operation to reduce threshold voltage downshift for select gate transistors | Chun-Hung Lai, Rajdeep Gautam, Shih-Chung Lee | 2019-08-06 |
| 10276248 | Early ramp down of dummy word line voltage during read to suppress select gate transistor downshift | Vinh Diep | 2019-04-30 |
| 10256137 | Self-aligned trench isolation in integrated circuits | Lei Xue, Kenichi Ohtsuka, Simon S. Chan, Rinji Sugino | 2019-04-09 |
| 10249372 | Reducing hot electron injection type of read disturb in 3D memory device during signal switching transients | Hong-Yan Chen, Wei Zhao, Yingda Dong | 2019-04-02 |
| 10235294 | Pre-read voltage pulse for first read error handling | Swaroop Kaza, Piyush Sagdeo | 2019-03-19 |
| 10204689 | Non-volatile memory with methods to reduce creep-up field between dummy control gate and select gate | Anubhav Khandelwal, Changyuan Chen, Cynthia Hsu, Yingda Dong | 2019-02-12 |
| 10121552 | Reducing charge loss in data memory cell adjacent to dummy memory cell | Ashish Baraskar, Liang Pang, Yingda Dong, Nan Lu, Hong-Yan Chen | 2018-11-06 |
| 10115737 | Charge storage region in non-volatile memory | Hoon Cho, Jun Wan | 2018-10-30 |
| 10115464 | Electric field to reduce select gate threshold voltage shift | Yingda Dong | 2018-10-30 |
| 10068651 | Channel pre-charge to suppress disturb of select gate transistors during erase in memory | Vinh Diep, Wei Zhao, Ashish Baraskar, Yingda Dong | 2018-09-04 |
| 10020314 | Forming memory cell film in stack opening | Ashish Baraskar, Liang Pang, Yanli Zhang, Yingda Dong | 2018-07-10 |
| 10008271 | Programming of dummy memory cell to reduce charge loss in select gate transistor | Vinh Diep, Yingda Dong | 2018-06-26 |
| 9899410 | Charge storage region in non-volatile memory | Hoon Cho, Jun Wan | 2018-02-20 |
| 9852803 | Dummy word line control scheme for non-volatile memory | Vinh Diep, Liang Pang, Yingda Dong | 2017-12-26 |
| 9830963 | Word line-dependent and temperature-dependent erase depth | Liang Pang, Vinh Diep, Yingda Dong | 2017-11-28 |
| 9831118 | Reducing neighboring word line in interference using low-k oxide | Liang Pang, Yingda Dong, Jayavel Pachamuthu | 2017-11-28 |
| 9831114 | Self-aligned trench isolation in integrated circuits | Lei Xue, Kenichi Ohtsuka, Rinji Sugino, Simon S. Chan | 2017-11-28 |
| 9779948 | Method of fabricating 3D NAND | Ashish Baraskar, Yanli Zhang, Zhenyu Lu | 2017-10-03 |
| 9761320 | Reducing hot electron injection type of read disturb during read recovery phase in 3D memory | Hong-Yan Chen, Wei Zhao | 2017-09-12 |
| 9748266 | Three-dimensional memory device with select transistor having charge trapping gate dielectric layer and methods of making and operating thereof | Ashish Baraskar, Yanli Zhang, Liang Pang, Matthias Baenninger, Yingda Dong | 2017-08-29 |
| 9728551 | Multi-tier replacement memory stack structure integration scheme | Zhenyu Lu, Jixin Yu, Daxin Mao, Johann Alsmeier, Wenguang Shi +1 more | 2017-08-08 |