Issued Patents All Time
Showing 25 most recent of 88 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12424557 | Dual structured buried rail | Huai Huang, Ruilong Xie, Hosadurga Shobha, Lawrence A. Clevenger | 2025-09-23 |
| 12424549 | Skip-level TSV with hybrid dielectric scheme for backside power delivery | Ruilong Xie, Huai Huang, Hosadurga Shobha, Lawrence A. Clevenger | 2025-09-23 |
| 12424550 | Buried metal signal rail for memory arrays | Biswanath Senapati, Seiji Munetoh, Lawrence A. Clevenger, Geoffrey Burr, Kohji Hosokawa | 2025-09-23 |
| 12417974 | Decoupling capacitance in backside interconnect | Rajiv V. Joshi, Ruilong Xie | 2025-09-16 |
| 12417979 | Pass-through wiring in notched interconnect | Albert M. Chu, Ruilong Xie, Reinaldo Vega, Lawrence A. Clevenger, Brent A. Anderson | 2025-09-16 |
| 12417963 | Isolation rail between backside power rails | Lawrence A. Clevenger, Hosadurga Shobha, Ruilong Xie, Baozhen Li | 2025-09-16 |
| 12412836 | Backside power plane | Ruilong Xie, Hosadurga Shobha, Lawrence A. Clevenger, Huai Huang | 2025-09-09 |
| 12412833 | TopVia interconnect with enlarged via top | Lawrence A. Clevenger, Chen Zhang, Brent A. Anderson | 2025-09-09 |
| 12400960 | Vertical-transport field-effect transistor with backside gate contact | Brent A. Anderson, Albert M. Chu, Ruilong Xie, Lawrence A. Clevenger, Reinaldo Vega | 2025-08-26 |
| 12387937 | Sam formulations and cleaning to promote quick depositions | Rudy J. Wojtecki, Prasad Bhosale, Son V. Nguyen | 2025-08-12 |
| 12363965 | Stacked transistor layout for improved cell height scaling | Ruilong Xie, Albert M. Chu, Daniel James Dechene, Eric Miller, Lawrence A. Clevenger | 2025-07-15 |
| 12334442 | Dielectric caps for power and signal line routing | Ruilong Xie, Lawrence A. Clevenger, Hosadurga Shobha, Huai Huang | 2025-06-17 |
| 12293140 | Feed-forward design of three-dimensional quantum chips | Marco Facchini, Zlatko Kristev Minev, Thomas George McConkey, Priti Ashvin Shah | 2025-05-06 |
| 12266393 | Negative capacitance for ferroelectric capacitive memory cell | Takashi Ando, Reinaldo Vega, David Wolpert | 2025-04-01 |
| 12261056 | Top via patterning using metal as hard mask and via conductor | Huai Huang, Hosadurga Shobha, Lawrence A. Clevenger, Chanro Park | 2025-03-25 |
| 12243819 | Single-mask alternating line deposition | Brent A. Anderson, Lawrence A. Clevenger, Christopher J. Penny, Kisik Choi, Robert R. Robison | 2025-03-04 |
| 12156486 | Horizontal RRAM device and architecture for variability reduction | Timothy Mathew Philip, Christopher J. Penny, Youngseok Kim, Lawrence A. Clevenger | 2024-11-26 |
| 12148682 | Memory cell in wafer backside | Biswanath Senapati, Seiji Munetoh, Lawrence A. Clevenger, Geoffrey Burr, Kohji Hosokawa | 2024-11-19 |
| 12142525 | Self-aligning spacer tight pitch via | Lawrence A. Clevenger, Brent A. Anderson | 2024-11-12 |
| 12040373 | Liner-free resistance contacts and silicide with silicide stop layer | Nicolas Loubet, Christian Lavoie, Adra Carr | 2024-07-16 |
| 11990410 | Top via interconnect having a line with a reduced bottom dimension | Brent A. Anderson, Lawrence A. Clevenger, Christopher J. Penny, Kisik Choi, Robert R. Robison | 2024-05-21 |
| 11961759 | Interconnects having spacers for improved top via critical dimension and overlay tolerance | Brent A. Anderson, Lawrence A. Clevenger, Christopher J. Penny, Kisik Choi, Robert R. Robison | 2024-04-16 |
| 11908791 | Partial subtractive supervia enabling hyper-scaling | Sagarika Mukesh | 2024-02-20 |
| 11908738 | Interconnect including integrally formed capacitor | Chih-Chao Yang | 2024-02-20 |
| 11894265 | Top via with damascene line and via | Lawrence A. Clevenger, Brent A. Anderson, Kisik Choi, Christopher J. Penny, Robert R. Robison | 2024-02-06 |