Issued Patents All Time
Showing 1–25 of 209 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12432968 | Nanowire source/drain formation for nanosheet device | Ruilong Xie, Kangguo Cheng, Alexander Reznicek | 2025-09-30 |
| 12426338 | Buried power rail with robust connection to a wrap around contact | Ruilong Xie, Kangguo Cheng, Chanro Park | 2025-09-23 |
| 12426314 | Strain generation and anchoring in gate-all-around field effect transistors | Sung-Dae Suk, Kangguo Cheng, Andrew M. Greene, Ruilong Xie | 2025-09-23 |
| 12419080 | Semiconductor structure with wrapped-around backside contact | Ruilong Xie, Chanro Park, Min Gyu Sung, Kangguo Cheng | 2025-09-16 |
| 12412829 | Method and structure of forming sidewall contact for stacked FET | Ruilong Xie, Su Chen Fan, Ravikumar Ramachandran, Oleg Gluschenkov | 2025-09-09 |
| 12414328 | Co-integrating gate-all-around nanosheet transistors and comb-nanosheet transistors | Huimei Zhou, Nicolas Loubet, Ruilong Xie, Miaomiao Wang, Veeraraghavan S. Basker | 2025-09-09 |
| 12414336 | Semiconductor structure having stacked power rails | Huimei Zhou, Ruilong Xie, Miaomiao Wang | 2025-09-09 |
| 12412830 | Semiconductor device with power via | Ruilong Xie, Junli Wang, Kisik Choi, Reinaldo Vega, Lawrence A. Clevenger +2 more | 2025-09-09 |
| 12402408 | Stacked FETS including devices with thick gate oxide | Ruilong Xie, Nicolas Loubet, Junli Wang, Ruqiang Bao, Min Gyu Sung +2 more | 2025-08-26 |
| 12396227 | Full wrap around backside contact | Ruilong Xie, Kisik Choi, Junli Wang, Min Gyu Sung | 2025-08-19 |
| 12389813 | Resistive switching memory cell | Kangguo Cheng, Ruilong Xie, Chanro Park | 2025-08-12 |
| 12389609 | Circuit architecture using transistors with dynamic dual functionality for logic and embedded memory drivers | Ruilong Xie, Kangguo Cheng, Heng Wu, Min Gyu Sung, Chanro Park | 2025-08-12 |
| 12382665 | Increased gate length at given footprint for nanosheet device | Ruilong Xie, Kangguo Cheng, Chanro Park | 2025-08-05 |
| 12382682 | Gate-all-around nanosheet-FET with variable channel geometries for performance optimization | Ruilong Xie, Heng Wu, Chen Zhang, Alexander Reznicek | 2025-08-05 |
| 12382662 | Wrap-around-contact for 2D-channel gate-all-around field-effect-transistors | Ruilong Xie, Kangguo Cheng, Chanro Park, Andrew Gaul | 2025-08-05 |
| 12363977 | Forming dielectric sidewall and bottom dielectric isolation in Fork-FET devices | Ruilong Xie, Kangguo Cheng, Dimitri Houssameddine | 2025-07-15 |
| 12362004 | Scaled 2T DRAM | Min Gyu Sung, Ruilong Xie, Chanro Park, Juntao Li | 2025-07-15 |
| 12349457 | Stacked transistors having bottom contact with replacement spacer | Kangguo Cheng, Ruilong Xie, Heng Wu | 2025-07-01 |
| 12336294 | Gate-cut and separation techniques for enabling independent gate control of stacked transistors | Ruilong Xie, Nicolas Loubet, Lawrence A. Clevenger, Prasad Bhosale, Junli Wang +2 more | 2025-06-17 |
| 12336279 | Fin stack including tensile-strained and compressively strained fin portions | Kangguo Cheng, Ruilong Xie, Chanro Park | 2025-06-17 |
| 12328916 | CPP-agnostic source-drain contact formation for gate-all-around devices with dielectric isolation | Ruilong Xie, Kangguo Cheng, Chanro Park, Oleg Gluschenkov | 2025-06-10 |
| 12328859 | Stacked FET SRAM | Ruilong Xie, Carl Radens, Albert M. Chu, Brent A. Anderson, Junli Wang +1 more | 2025-06-10 |
| 12324234 | Fork sheet device with better electrostatic control | Ruilong Xie, Kangguo Cheng, Chanro Park | 2025-06-03 |
| 12324207 | Channel protection of gate-all-around devices for performance optimization | Maruf Amin Bhuiyan, Ruilong Xie, Eric Miller | 2025-06-03 |
| 12324197 | Spin-based gate-all-around transistors | Kangguo Cheng, Ruilong Xie, Chanro Park, Andrew Gaul, Min Gyu Sung | 2025-06-03 |