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Method and structure for integrating photonics with CMOs |
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2018-01-23 |
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Integrated circuit (IC) design analysis and feature extraction |
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2017-09-05 |
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Method and structure to reduce FET threshold voltage shift due to oxygen diffusion |
Michael P. Chudzik, Deleep R. Nair, Jay M. Shah |
2016-08-30 |
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Method and structure to reduce FET threshold voltage shift due to oxygen diffusion |
Michael P. Chudzik, Deleep R. Nair, Jay M. Shah |
2015-07-28 |
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Process variability tolerant hard mask for replacement metal gate finFET devices |
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2015-05-19 |
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Metal oxide semiconductor field effect transistor (MOSFET) gate termination |
Daniel Jaeger, Carl Radens, Helen Wang |
2014-04-22 |
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Metal oxide semiconductor field effect transistor (MOSFET) gate termination |
Daniel Jaeger, Carl Radens, Helen Wang |
2014-01-14 |
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Spacer and process to enhance the strain in the channel with stress liner |
Atul Ajmera, Xiangdong Chen, Wenzhi Gao, Young Way Teh |
2013-06-11 |
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CMOS SiGe channel pFET and Si channel nFET devices with minimal STI recess |
Daniel Jaeger, Michael V. Aquilino |
2011-11-08 |
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Method for transistor fabrication with optimized performance |
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2011-02-08 |
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Method for improved fabrication of a semiconductor using a stress proximity technique process |
Xiangdong Chen, Wenzhi Gao, Young-Gun Ko, Young Way Teh |
2009-05-12 |
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Dual layer stress liner for MOSFETS |
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2009-04-21 |
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Structure of static random access memory with stress engineering for stability |
Xiangdong Chen, Young-Gun Ko, Melanie J. Sherony |
2008-12-30 |
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Trench sidewall passivation for lateral RIE in a selective silicon-on-insulator process flow |
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2006-07-25 |