Issued Patents All Time
Showing 25 most recent of 41 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11239077 | Litho-etch-litho-etch with self-aligned blocks | Chi-Chun Liu, Nelson Felix, Yann Mignot, Ekmini Anuja De Silva, John C. Arnold | 2022-02-01 |
| 10552569 | Method for calculating non-correctable EUV blank flatness for blank dispositioning | Christina A. Turley, Jed H. Rankin, Xuemei Chen, Timothy A. Brunner | 2020-02-04 |
| 10242952 | Registration mark formation during sidewall image transfer process | David J. Conklin, Sivananda K. Kanakasabapathy, Byeong Y. Kim, Fee Li Lie, Stuart A. Sieg | 2019-03-26 |
| 10043760 | Registration mark formation during sidewall image transfer process | David J. Conklin, Sivananda K. Kanakasabapathy, Byeong Y. Kim, Fee Li Lie, Stuart A. Sieg | 2018-08-07 |
| 9859224 | Registration mark formation during sidewall image transfer process | David J. Conklin, Sivananda K. Kanakasabapathy, Byeong Y. Kim, Fee Li Lie, Stuart A. Sieg | 2018-01-02 |
| 9472506 | Registration mark formation during sidewall image transfer process | David J. Conklin, Sivananda K. Kanakasabapathy, Byeong Y. Kim, Fee Li Lie, Stuart A. Sieg | 2016-10-18 |
| 9360858 | Alignment data based process control system | Christopher P. Ausschnitt, Timothy A. Brunner, Oleg Gluschenkov, Vinayan C. Menon | 2016-06-07 |
| 9046788 | Method for monitoring focus on an integrated wafer | Wai-Kin Li | 2015-06-02 |
| 8847416 | Multi-layer chip overlay target and measurement | Christopher P. Ausschnitt, Nelson Felix | 2014-09-30 |
| 8673165 | Sidewall image transfer process with multiple critical dimensions | Sudharshanan Raghunathan, Sivananda K. Kanakasabapathy, Ryan O. Jung, Sean D. Burns, Erin Catherine McLellan | 2014-03-18 |
| 8609322 | Process of making a lithographic structure using antireflective materials | Marie Angelopoulos, Katherina Babich, Sean D. Burns, Scott D. Halle, Arpan Mahorowala +1 more | 2013-12-17 |
| 8592110 | Alignment marks for multi-exposure lithography | Vinayan C. Menon | 2013-11-26 |
| 8507346 | Method of forming a semiconductor device having a cut-way hole to expose a portion of a hardmask layer | Martin Burkhardt, Matthew E. Colburn, Oleg Gluschenkov, Scott D. Halle, Howard S. Landis +1 more | 2013-08-13 |
| 8491984 | Structure resulting from chemical shrink process over BARC (bottom anti-reflective coating) | Todd C. Bailey, Colin J. Brodsky | 2013-07-23 |
| 8455162 | Alignment marks for multi-exposure lithography | Vinayan C. Menon | 2013-06-04 |
| 8361683 | Multi-layer chip overlay target and measurement | Christopher P. Ausschnitt, Nelson Felix | 2013-01-29 |
| 8293454 | Process of making a lithographic structure using antireflective materials | Marie Angelopoulos, Katherina Babich, Sean D. Burns, Scott D. Halle, Arpan Mahorowala +1 more | 2012-10-23 |
| 8158334 | Methods for forming a composite pattern including printed resolution assist features | Scott D. Halle, Helen Wang | 2012-04-17 |
| 8110496 | Method for performing chemical shrink process over BARC (bottom anti-reflective coating) | Todd C. Bailey, Colin J. Brodsky | 2012-02-07 |
| 8039203 | Integrated circuits and methods of design and manufacture thereof | Helen Wang, Scott D. Halle, Henning Haffner, Haoren Zhuang, Klaus Herold +4 more | 2011-10-18 |
| 7993815 | Line ends forming | Matthew E. Colburn, Scott D. Halle, Donald J. Samuels | 2011-08-09 |
| 7968270 | Process of making a semiconductor device using multiple antireflective materials | Marie Angelopoulos, Katherina Babich, Sean D. Burns, Richard A. Conti, Scott D. Halle +2 more | 2011-06-28 |
| 7914975 | Multiple exposure lithography method incorporating intermediate layer patterning | Sean D. Burns, Scott D. Halle, Dirk Pfeiffer | 2011-03-29 |
| 7799503 | Composite structures to prevent pattern collapse | Colin J. Brodsky, Javier Perez | 2010-09-21 |
| 7727825 | Polyconductor line end formation and related mask | Shahid Butt, Donald J. Samuels | 2010-06-01 |