| 12218041 |
Integrated circuit (IC) packages employing a capacitor-embedded, redistribution layer (RDL) substrate for interfacing an IC chip(s) to a package substrate, and related methods |
Jihong Choi, Giridhar Nallapati, William Stone, Jianwen Xu, Jonghae Kim +1 more |
2025-02-04 |
| 10327076 |
Top port MEMS package and method |
Bob Shih-Wei Kuo, Louis B. Troche, Jr. |
2019-06-18 |
| 10236268 |
Robust pillar structure for semicondcutor device contacts |
Karthikeyan Dhandapani, Sundeep Nand Nangalia |
2019-03-19 |
| 9806063 |
Reinforced wafer level package comprising a core layer for reducing stress in a solder joint and improving solder joint reliability |
Chin-Kwan Kim, Rajneesh Kumar, Vladimir Noveski, Jie Fu, Milind Shah +1 more |
2017-10-31 |
| 9484291 |
Robust pillar structure for semicondcutor device contacts |
Karthikeyan Dhandapani, Sundeep Nand Nangalia |
2016-11-01 |
| 9420378 |
Top port MEMS microphone package and method |
Bob Shih-Wei Kuo, Louis B. Troche, Jr. |
2016-08-16 |
| 9379090 |
System, apparatus, and method for split die interconnection |
Chin-Kwan Kim, Omar J. Bchir, Milind Shah, Ryan David Lane |
2016-06-28 |
| 9013011 |
Stacked and staggered die MEMS package and method |
Bob Shih-Wei Kuo, Brett Dunlap, Louis B. Troche, Jr., Russell Shumway |
2015-04-21 |
| 8912051 |
Method for controlling molding compound geometry around a semiconductor die |
Miguel A. Jimarez, Jeff Watson |
2014-12-16 |
| 8217507 |
Edge mount semiconductor package |
Jesse E. Galloway, Bob Shih-Wei Kuo |
2012-07-10 |
| 7183630 |
Lead frame with plated end leads |
Harry J. Fogelson, Ludcvico Estrada Bancod, Terry Davis, Primitivo A. Palasi, William M. Anderson |
2007-02-27 |
| 6885086 |
Reduced copper lead frame for saw-singulated chip package |
Harry J. Fogelson, Ludovico E. Bancod, Gregorio G. Dela Cruz, Primitivo A. Palasi, William M. Anderson |
2005-04-26 |
| 6608366 |
Lead frame with plated end leads |
Harry J. Fogelson, Ludovico E. Bancod, Terry Davis, Primitivo A. Palasi, William M. Anderson |
2003-08-19 |
| 5491364 |
Reduced stress terminal pattern for integrated circuit devices and packages |
Scott D. Brandenburg, William S. Murphy, David King, Shing Yeh |
1996-02-13 |