Issued Patents All Time
Showing 176–200 of 250 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10644140 | Integrated circuit die having back-end-of-line transistors | Gilbert Dewey, Marko Radosavljevic, Rafael Rios, Jack T. Kavalieros | 2020-05-05 |
| 10593785 | Transistors having ultra thin fin profiles and their methods of fabrication | Sanaz K. Gardner, Willy Rachmady, Matthew V. Metz, Seiyon Kim, Ashish Agrawal +1 more | 2020-03-17 |
| 10580882 | Low band gap semiconductor devices having reduced gate induced drain leakage (GIDL) | Gilbert Dewey, Jack T. Kavalieros, Willy Rachmady, Matthew V. Metz, Seiyon Kim +1 more | 2020-03-03 |
| 10565138 | Memory device with multiple memory arrays to facilitate in-memory computation | Jack T. Kavalieros, Ram Krishnamurthy, Sasikanth Manipatruni, Gregory K. Chen, Amrita Mathuriya +5 more | 2020-02-18 |
| 10475706 | Making a defect free fin based device in lateral epitaxy overgrowth region | Niti Goel, Benjamin Chu-Kung, Sansaptak Dasgupta, Niloy Mukherjee, Matthew V. Metz +3 more | 2019-11-12 |
| 10418487 | Non-planar gate all-around device and method of fabrication thereof | Willy Rachmady, Ravi Pillarisetty, Jack T. Kavalieros, Robert S. Chau, Jessica S. Kachian | 2019-09-17 |
| 10403733 | Dielectric metal oxide cap for channel containing germanium | Gilbert Dewey, Ashish Agrawal, Benjamin Chu-Kung, Matthew V. Metz, Willy Rachmady +2 more | 2019-09-03 |
| 10388800 | Thin film transistor with gate stack on multiple sides | Seung Hoon Sung, Abhishek A. Sharma, Gilbert Dewey, Jack T. Kavalieros, Tahir Ghani | 2019-08-20 |
| 10388733 | Strain compensation in transistors | Benjamin Chu-Kung, Harold Hal W. Kennel, Willy Rachmady, Ravi Pillarisetty, Jack T. Kavalieros | 2019-08-20 |
| 10347767 | Transistor with a subfin layer | Willy Rachmady, Matthew V. Metz, Ravi Pillarisetty, Gilbert Dewey, Jack T. Kavalieros +1 more | 2019-07-09 |
| 10340275 | Stackable thin film memory | Elijah V. Karpov, Jack T. Kavalieros, Robert S. Chau, Niloy Mukherjee, Rafael Rios +5 more | 2019-07-02 |
| 10319646 | CMOS implementation of germanium and III-V nanowires and nanoribbons in gate-all-around architecture | Marko Radosavljevic, Ravi Pillarisetty, Gilbert Dewey, Niloy Mukherjee, Jack T. Kavalieros +4 more | 2019-06-11 |
| 10249490 | Non-silicon device heterolayers on patterned silicon substrate for CMOS by combination of selective and conformal epitaxy | Niti Goel, Robert S. Chau, Jack T. Kavalieros, Benjamin Chu-Kung, Matthew V. Metz +7 more | 2019-04-02 |
| 10249740 | Ge nano wire transistor with GaAs as the sacrificial layer | Willy Rachmady, Matthew V. Metz, Jack T. Kavalieros, Sanaz K. Gardner | 2019-04-02 |
| 10249742 | Offstate parasitic leakage reduction for tunneling field effect transistors | Gilbert Dewey, Benjamin Chu-Kung, Ashish Agrawal, Matthew V. Metz, Willy Rachmady +8 more | 2019-04-02 |
| 10224399 | Strain compensation in transistors | Benjamin Chu-Kung, Harold Hal W. Kennel, Willy Rachmady, Ravi Pillarisetty, Jack T. Kavalieros | 2019-03-05 |
| 10204989 | Method of fabricating semiconductor structures on dissimilar substrates | Benjamin Chu-Kung, Sherry R. Taft, Sansaptak Dasgupta, Seung Hoon Sung, Sanaz K. Gardner +3 more | 2019-02-12 |
| 10186580 | Semiconductor device having germanium active layer with underlying diffusion barrier layer | Willy Rachmady, Ravi Pillarisetty, Jack T. Kavalieros, Robert S. Chau, Harold W. Kennel | 2019-01-22 |
| 10103263 | Strained channel region transistors employing source and drain stressors and systems including the same | Harold W. Kennel, Willy Rachmady, Ravi Pillarisetty, Jack T. Kavalieros, Niloy Mukherjee | 2018-10-16 |
| 10096709 | Aspect ratio trapping (ART) for fabricating vertical semiconductor devices | Benjamin Chu-Kung, Gilbert Dewey, Jack T. Kavalieros, Ravi Pillarisetty, Willy Rachmady +4 more | 2018-10-09 |
| 10038054 | Variable gate width for gate all-around transistors | Willy Rachmady, Ravi Pillarisetty, Jack T. Kavalieros, Robert S. Chau, Seung Hoon Sung | 2018-07-31 |
| 10026845 | Deep gate-all-around semiconductor device having germanium or group III-V active layer | Ravi Pillarisetty, Willy Rachmady, Seung Hoon Sung, Jessica S. Kachian, Jack T. Kavalieros +5 more | 2018-07-17 |
| 10020371 | Contact techniques and configurations for reducing parasitic resistance in nanowire transistors | Ravi Pillarisetty, Benjamin Chu-Kung, Willy Rachmady, Gilbert Dewey, Niloy Mukherjee +3 more | 2018-07-10 |
| 10008565 | Semiconductor devices with germanium-rich active layers and doped transition layers | Willy Rachmady, Ravi Pillarisetty, Jessica S. Kachian, Marc C. French, Aaron A. Budrevich | 2018-06-26 |
| 9972686 | Germanium tin channel transistors | Ravi Pillarisetty, Willy Rachmady, Roza Kotlyar, Marko Radosavljevic, Han Wui Then +4 more | 2018-05-15 |