Issued Patents All Time
Showing 151–175 of 250 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10950301 | Two transistor, one resistor non-volatile gain cell memory and storage element | Rafael Rios, Abhishek A. Sharma, Gilbert Dewey, Jack T. Kavalieros | 2021-03-16 |
| 10942562 | Methods and apparatus to manage operation of variable-state computing devices using artificial intelligence | Shekoufeh Qawami, Nageen Himayat, Chaitanya Sreerama, Hassnaa Moustafa, Rita H. Wouhaybi +4 more | 2021-03-09 |
| 10930791 | Systems, methods, and apparatuses for implementing bi-layer semiconducting oxides in source and drain for low access and contact resistance of thin film transistors | Gilbert Dewey, Rafael Rios, Shriram Shivaraman, Jack T. Kavalieros, Marko Radosavljevic | 2021-02-23 |
| 10930766 | Ge NANO wire transistor with GAAS as the sacrificial layer | Willy Rachmady, Matthew V. Metz, Jack T. Kavalieros, Sanaz K. Gardner | 2021-02-23 |
| 10930679 | Thin film transistors with a crystalline oxide semiconductor source/drain | Gilbert Dewey, Abhishek A. Sharma, Shriram Shivaraman, Ravi Pillarisetty, Tahir Ghani | 2021-02-23 |
| 10878889 | High retention time memory element with dual gate devices | Rafael Rios, Gilbert Dewey, Jack T. Kavalieros, Mesut Meterelliyoz | 2020-12-29 |
| 10872660 | Resistive memory devices with transition metal dichalcogenide (TMD) materials as ballast resistors to control current flow through the devices | Abhishek A. Sharma, Ravi Pillarisetty, Gilbert Dewey | 2020-12-22 |
| 10847656 | Fabrication of non-planar IGZO devices for improved electrostatics | Gilbert Dewey, Rafael Rios, Jack T. Kavalieros, Marko Radosavljevic, Kent Millard +4 more | 2020-11-24 |
| 10818799 | Vertical transistor devices and techniques | Ravi Pillarisetty, Abhishek A. Sharma, Gilbert Dewey, Willy Rachmady | 2020-10-27 |
| 10811461 | Access transmission gate | Abhishek A. Sharma, Ravi Pillarisetty, Gilbert Dewey | 2020-10-20 |
| 10784352 | Method to achieve a uniform Group IV material layer in an aspect ratio trapping trench | Sanaz K. Gardner, Willy Rachmady, Matthew V. Metz, Seiyon Kim, Ashish Agrawal +1 more | 2020-09-22 |
| 10784170 | CMOS implementation of germanium and III-V nanowires and nanoribbons in gate-all-around architecture | Marko Radosavljevic, Ravi Pillarisetty, Gilbert Dewey, Niloy Mukherjee, Jack T. Kavalieros +4 more | 2020-09-22 |
| 10763349 | Quantum dot devices with modulation doped stacks | Ravi Pillarisetty, Jeanette M. Roberts, James S. Clarke, Zachary R. Yoscovits, David J. Michalak | 2020-09-01 |
| 10763347 | Quantum well stacks for quantum dot devices | Payam Amin, Nicole K. Thomas, James S. Clarke, Jessica M. Torres, Ravi Pillarisetty +6 more | 2020-09-01 |
| 10748993 | Strain compensation in transistors | Benjamin Chu-Kung, Harold Hal W. Kennel, Willy Rachmady, Ravi Pillarisetty, Jack T. Kavalieros | 2020-08-18 |
| 10734488 | Aluminum indium phosphide subfin germanium channel transistors | Matthew V. Metz, Willy Rachmady, Harold W. Kennel, Benjamin Chu-Kung, Jack T. Kavalieros +1 more | 2020-08-04 |
| 10727339 | Selectively regrown top contact for vertical semiconductor devices | Benjamin Chu-Kung, Gilbert Dewey, Jack T. Kavalieros, Marko Radosavljevic, Ravi Pillarisetty +3 more | 2020-07-28 |
| 10727138 | Integration of single crystalline transistors in back end of line (BEOL) | Marko Radosavljevic, Benjamin Chu-Kung, Rafael Rios, Gilbert Dewey | 2020-07-28 |
| 10720508 | Fabrication of multi-channel nanowire devices with self-aligned internal spacers and SOI FinFETs using selective silicon nitride capping | Scott B. Clendenning, Martin M. Mitan, Szuya S. Liao | 2020-07-21 |
| 10693008 | Cladding layer epitaxy via template engineering for heterogeneous integration on silicon | Niloy Mukherjee, Marko Radosavljevic, Jack T. Kavalieros, Ravi Pillarisetty, Niti Goel +2 more | 2020-06-23 |
| 10665688 | Low Schottky barrier contact structure for Ge NMOS | Willy Rachmady, Matthew V. Metz, Benjamin Chu-Kung, Gilbert Dewey, Ashish Agrawal +1 more | 2020-05-26 |
| 10659046 | Local cell-level power gating switch | Rafael Rios, Gilbert Dewey, Jack T. Kavalieros | 2020-05-19 |
| 10644123 | Systems, methods, and apparatuses for implementing a high mobility low contact resistance semiconducting oxide in metal contact vias for thin film transistors | Gilbert Dewey, Rafael Rios, Jack T. Kavalieros, Shriram Shivaraman | 2020-05-05 |
| 10644111 | Strained silicon layer with relaxed underlayer | Benjamin Chu-Kung, Ashish Agrawal, Jack T. Kavalieros, Matthew V. Metz, Seung Hoon Sung +2 more | 2020-05-05 |
| 10644112 | Systems, methods and devices for isolation for subfin leakage | Benjamin Chu-Kung, Seung Hoon Sung, Jack T. Kavalieros, Ashish Agrawal, Harold W. Kennel +5 more | 2020-05-05 |