Issued Patents All Time
Showing 76–100 of 304 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11049773 | Art trench spacers to enable fin release for non-lattice matched channels | Gilbert Dewey, Sean T. Ma, Cheng-Ying Huang, Tahir Ghani, Anand S. Murthy +4 more | 2021-06-29 |
| 11031499 | Germanium transistor structure with underlap tip to reduce gate induced barrier lowering/short channel effect while minimizing impact on drive current | Willy Rachmady, Van H. Le, Benjamin Chu-Kung, Ashish Agrawal, Jack T. Kavalieros | 2021-06-08 |
| 11031482 | Gate electrode having a capping layer | Gilbert Dewey, Mark L. Doczy, Suman Datta, Justin K. Brask | 2021-06-08 |
| 11017843 | Thin film transistors for memory cell array layer selection | Abhishek A. Sharma, Gilbert Dewey, Willy Rachmady, Van H. Le, Jack T. Kavalieros | 2021-05-25 |
| 10957769 | High-mobility field effect transistors with wide bandgap fin cladding | Sean T. Ma, Chandra S. Mohapatra, Gilbert Dewey, Willy Rachmady, Harold W. Kennel +3 more | 2021-03-23 |
| 10937907 | Method for fabricating transistor with thinned channel | Justin K. Brask, Robert S. Chau, Suman Datta, Mark L. Doczy, Brian S. Doyle +3 more | 2021-03-02 |
| 10930766 | Ge NANO wire transistor with GAAS as the sacrificial layer | Willy Rachmady, Van H. Le, Jack T. Kavalieros, Sanaz K. Gardner | 2021-02-23 |
| 10903364 | Semiconductor device with released source and drain | Willy Rachmady, Sanaz K. Gardner, Chandra S. Mohapatra, Gilbert Dewey, Sean T. Ma +3 more | 2021-01-26 |
| 10892335 | Device isolation by fixed charge | Sean T. Ma, Willy Rachmady, Gilbert Dewey, Aaron D. Lilak, Justin R. Weber +5 more | 2021-01-12 |
| 10886408 | Group III-V material transistors employing nitride-based dopant diffusion barrier layer | Chandra S. Mohapatra, Harold W. Kennel, Glenn A. Glass, Willy Rachmady, Anand S. Murthy +4 more | 2021-01-05 |
| 10879365 | Transistors with non-vertical gates | Cheng-Ying Huang, Sean T. Ma, Willy Rachmady, Gilbert Dewey, Harold W. Kennel +3 more | 2020-12-29 |
| 10861939 | Stiff quantum layers to slow and or stop defect propagation | Gilbert Dewey, Harold W. Kennel, Cheng-Ying Huang, Sean T. Ma, Willy Rachmady | 2020-12-08 |
| 10847619 | Supperlatice channel included in a trench | Cheng-Ying Huang, Willy Rachmady, Gilbert Dewey, Jack T. Kavalieros | 2020-11-24 |
| 10818793 | Indium-rich NMOS transistor channels | Chandra S. Mohapatra, Anand S. Murthy, Glenn A. Glass, Tahir Ghani, Willy Rachmady +3 more | 2020-10-27 |
| 10797150 | Differential work function between gate stack metals to reduce parasitic capacitance | Sean T. Ma, Willy Rachmady, Chandra S. Mohapatra, Gilbert Dewey, Nadia M. Rahhal-Orabi +3 more | 2020-10-06 |
| 10784170 | CMOS implementation of germanium and III-V nanowires and nanoribbons in gate-all-around architecture | Marko Radosavljevic, Ravi Pillarisetty, Gilbert Dewey, Niloy Mukherjee, Jack T. Kavalieros +4 more | 2020-09-22 |
| 10784352 | Method to achieve a uniform Group IV material layer in an aspect ratio trapping trench | Sanaz K. Gardner, Willy Rachmady, Van H. Le, Seiyon Kim, Ashish Agrawal +1 more | 2020-09-22 |
| 10770593 | Beaded fin transistor | Gilbert Dewey, Tahir Ghani, Willy Rachmady, Jack T. Kavalieros, Anand S. Murthy +1 more | 2020-09-08 |
| 10756198 | Fermi-level unpinning structures for semiconductive devices, processes of forming same, and systems containing same | Gilbert Dewey, Niloy Mukherjee, Jack T. Kavalieros, Nancy Zelick, Robert S. Chau | 2020-08-25 |
| 10748900 | Fin-based III-V/SI or GE CMOS SAGE integration | Willy Rachmady, Gilbert Dewey, Chandra S. Mohapatra, Jack T. Kavalieros, Anand S. Murthy +1 more | 2020-08-18 |
| 10734511 | High mobility asymmetric field effect transistors with a band-offset semiconductor drain spacer | Cheng-Ying Huang, Willy Rachmady, Jack T. Kavalieros, Benjamin Chu-Kung, Gilbert Dewey +1 more | 2020-08-04 |
| 10734488 | Aluminum indium phosphide subfin germanium channel transistors | Willy Rachmady, Harold W. Kennel, Van H. Le, Benjamin Chu-Kung, Jack T. Kavalieros +1 more | 2020-08-04 |
| 10707319 | Gate electrode having a capping layer | Gilbert Dewey, Mark L. Doczy, Suman Datta, Justin K. Brask | 2020-07-07 |
| 10665688 | Low Schottky barrier contact structure for Ge NMOS | Willy Rachmady, Benjamin Chu-Kung, Van H. Le, Gilbert Dewey, Ashish Agrawal +1 more | 2020-05-26 |
| 10651313 | Reduced transistor resistance using doped layer | Cheng-Ying Huang, Gilbert Dewey, Willy Rachmady, Jack T. Kavalieros, Sean T. Ma | 2020-05-12 |