Issued Patents All Time
Showing 101–125 of 256 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9646887 | Tailored silicon layers for transistor multi-gate control | John Rozen | 2017-05-09 |
| 9646886 | Tailored silicon layers for transistor multi-gate control | John Rozen | 2017-05-09 |
| 9634116 | Method to improve reliability of high-K metal gate stacks | Takashi Ando, Eduard A. Cartier, Barry P. Linder | 2017-04-25 |
| 9627508 | Replacement channel TFET | Michael P. Chudzik, Siddarth A. Krishnan, Unoh Kwon, Jeffrey W. Sleight | 2017-04-18 |
| 9608066 | High-K spacer for extension-free CMOS devices with high mobility channel materials | Takashi Ando, Pouya Hashemi, Yanning Sun | 2017-03-28 |
| 9590100 | Semiconductor devices containing an epitaxial perovskite/doped strontium titanate structure | Catherine A. Dubourdieu, Martin M. Frank | 2017-03-07 |
| 9589851 | Dipole-based contact structure to reduce metal-semiconductor contact resistance in MOSFETs | Huiming Bu, Hui-feng Li, Hiroaki Niimi, Tenko Yamashita | 2017-03-07 |
| 9583400 | Gate stack with tunable work function | Ruqiang Bao, Siddarth A. Krishnan, Unoh Kwon | 2017-02-28 |
| 9564505 | Changing effective work function using ion implantation during dual work function metal gate integration | Michael P. Chudzik, Martin M. Frank, Herbert L. Ho, Mark J. Hurley, Rashmi Jha +3 more | 2017-02-07 |
| 9559016 | Semiconductor device having a gate stack with tunable work function | Ruqiang Bao, Siddarth A. Krishnan, Unoh Kwon | 2017-01-31 |
| 9548381 | Method and structure for III-V nanowire tunnel FETs | Siddarth A. Krishnan, Unoh Kwon, Jeffrey W. Sleight | 2017-01-17 |
| 9484438 | Method to improve reliability of replacement gate device | Takashi Ando, Eduard A. Cartier, Kisik Choi | 2016-11-01 |
| 9472643 | Method to improve reliability of replacement gate device | Takashi Ando, Eduard A. Cartier, Kisik Choi | 2016-10-18 |
| 9472553 | High-K gate dielectric and metal gate conductor stack for planar field effect transistors formed on type III-V semiconductor material and silicon germanium semiconductor material | Takashi Ando, Martin M. Frank, Pranita Kerber | 2016-10-18 |
| 9466692 | Method to improve reliability of replacement gate device | Takashi Ando, Eduard A. Cartier, Kisik Choi | 2016-10-11 |
| 9455203 | Low threshold voltage CMOS device | Takashi Ando, Changhwan Choi, Kisik Choi | 2016-09-27 |
| 9449887 | Method of forming replacement gate PFET having TiALCO layer for improved NBTI performance | Takashi Ando, Balaji Kannan | 2016-09-20 |
| 9443953 | Sacrificial silicon germanium channel for inversion oxide thickness scaling with mitigated work function roll-off and improved negative bias temperature instability | Takashi Ando, Eduard A. Cartier, Kevin K. Chan | 2016-09-13 |
| 9397199 | Methods of forming multi-Vt III-V TFET devices | Unoh Kwon, Siddarth A. Krishnan, Jeffrey W. Sleight | 2016-07-19 |
| 9397175 | Multi-composition gate dielectric field effect transistors | Emre Alptekin, Unoh Kwon, Wing L. Lai, Zhengwen Li, Ravikumar Ramachandran +1 more | 2016-07-19 |
| 9391164 | Method to improve reliability of replacement gate device | Takashi Ando, Eduard A. Cartier, Kisik Choi | 2016-07-12 |
| 9368593 | Multiple thickness gate dielectrics for replacement gate field effect transistors | Unoh Kwon, Wing L. Lai, Sean M. Polvino, Ravikumar Ramachandran, Shahab Siddiqui | 2016-06-14 |
| 9362282 | High-K gate dielectric and metal gate conductor stack for planar field effect transistors formed on type III-V semiconductor material and silicon germanium semiconductor material | Takashi Ando, Martin M. Frank, Pranita Kerber | 2016-06-07 |
| 9349832 | Sacrificial silicon germanium channel for inversion oxide thickness scaling with mitigated work function roll-off and improved negative bias temperature instability | Takashi Ando, Eduard A. Cartier, Kevin K. Chan | 2016-05-24 |
| 9299802 | Method to improve reliability of high-K metal gate stacks | Takashi Ando, Eduard A. Cartier, Barry P. Linder | 2016-03-29 |