Issued Patents All Time
Showing 26–50 of 207 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10937793 | Vertical transistor contact for a memory cell with increased density | Brent A. Anderson, Junli Wang | 2021-03-02 |
| 10916478 | Methods of performing fin cut etch processes for FinFET semiconductor devices | Lei Zhuang, Balasubramanian Pranatharthiharan, Lars Liebmann, Ruilong Xie | 2021-02-09 |
| 10910282 | Prevention of charging damage in full-depletion devices | — | 2021-02-02 |
| 10910312 | Power distribution networks for monolithic three-dimensional semiconductor integrated circuit devices | Joshua M. Rubin | 2021-02-02 |
| 10903332 | Fully depleted SOI transistor with a buried ferroelectric layer in back-gate | Kangguo Cheng, Shawn P. Fetterolf | 2021-01-26 |
| 10903165 | Power distribution networks for monolithic three-dimensional semiconductor integrated circuit devices | Joshua M. Rubin | 2021-01-26 |
| 10840373 | Integration of input/output device in vertical field-effect transistor technology | Xuefeng Liu, Junli Wang, Brent A. Anderson, Gauri Karve | 2020-11-17 |
| 10833069 | Logic gate designs for 3D monolithic direct stacked VTFET | Chen Zhang, Tenko Yamashita | 2020-11-10 |
| 10748901 | Interlayer via contacts for monolithic three-dimensional semiconductor integrated circuit devices | Joshua M. Rubin, Nicolas Loubet | 2020-08-18 |
| 10741544 | Integration of electrostatic discharge protection into vertical fin technology | Brent A. Anderson, Huiming Bu, Xuefeng Liu, Junli Wang | 2020-08-11 |
| 10700209 | Independent gate FinFET with backside gate contact | Joshua M. Rubin, Tenko Yamashita | 2020-06-30 |
| 10691870 | Checking wafer-level integrated designs for rule compliance | Larry Wissel | 2020-06-23 |
| 10629443 | Bottom source/drain silicidation for vertical field-effect transistor (FET) | Brent A. Anderson, Huiming Bu, Fee Li Lie, Junli Wang | 2020-04-21 |
| 10615276 | Integration of input/output device in vertical field-effect transistor technology | Xuefeng Liu, Junli Wang, Brent A. Anderson, Gauri Karve | 2020-04-07 |
| 10615027 | Stack viabar structures | Su Chen Fan, Hsueh-Chung Chen, Yann Mignot, James J. Kelly | 2020-04-07 |
| 10608080 | Bulk to silicon on insulator device | Joshua M. Rubin, Tenko Yamashita | 2020-03-31 |
| 10607992 | Semiconductor device and method of forming the semiconductor device | Brent A. Anderson, Shawn P. Fetterolf | 2020-03-31 |
| 10607938 | Power distribution networks for monolithic three-dimensional semiconductor integrated circuit devices | Joshua M. Rubin | 2020-03-31 |
| 10586854 | Gate-all-around field effect transistor having multiple threshold voltages | Ruqiang Bao, Michael A. Guillorn, Robert R. Robison, Reinaldo Vega, Tenko Yamashita | 2020-03-10 |
| 10566453 | Vertical transistor contact for cross-coupling in a memory cell | Brent A. Anderson, Junli Wang | 2020-02-18 |
| 10559670 | Nanosheet field effect transistors with partial inside spacers | Michael A. Guillorn, Robert R. Robison, Reinaldo Vega, Rajasekhar Venigalla | 2020-02-11 |
| 10559572 | Vertical transistor contact for a memory cell with increased density | Brent A. Anderson, Junli Wang | 2020-02-11 |
| 10546787 | Multi-metal dipole doping to offer multi-threshold voltage pairs without channel doping for highly scaling CMOS device | Ruqiang Bao, Vijay Narayanan, Hemanth Jagannathan | 2020-01-28 |
| 10541253 | FinFETs with various fin height | Kangguo Cheng, Xin Miao, Balasubramanian Pranatharthiharan | 2020-01-21 |
| 10515859 | Extra gate device for nanosheet | Bruce B. Doris, Junli Wang | 2019-12-24 |