Issued Patents All Time
Showing 151–175 of 204 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8890255 | Structure and method for stress latching in non-planar semiconductor devices | Sanjay C. Mehta, Hemanth Jagannathan | 2014-11-18 |
| 8847338 | Method for forming a self-aligned hard mask for contact to a tunnel junction | Solomon Assefa | 2014-09-30 |
| 8835232 | Low external resistance ETSOI transistors | Hemanth Jagannathan | 2014-09-16 |
| 8802565 | Semiconductor plural gate lengths | Michael J. Hartig, Soon-Cheon Seo, Raghavasimhan Sreenivasan | 2014-08-12 |
| 8779515 | Semiconductor structure containing an aluminum-containing replacement gate electrode | David V. Horak, Hemanth Jagannathan | 2014-07-15 |
| 8753934 | Structure and method to integrate embedded DRAM with FinFET | Hemanth Jagannathan, Geng Wang | 2014-06-17 |
| 8741752 | Borderless contacts in semiconductor devices | Su Chen Fan, David V. Horak | 2014-06-03 |
| 8735296 | Method of simultaneously forming multiple structures having different critical dimensions using sidewall transfer | Ryan O. Jung | 2014-05-27 |
| 8673165 | Sidewall image transfer process with multiple critical dimensions | Sudharshanan Raghunathan, Ryan O. Jung, Allen H. Gabor, Sean D. Burns, Erin Catherine McLellan | 2014-03-18 |
| 8653610 | High performance non-planar semiconductor devices with metal filled inter-fin gaps | Hemanth Jagannathan | 2014-02-18 |
| 8637930 | FinFET parasitic capacitance reduction using air gap | Takashi Ando, Josephine B. Chang, Pranita Kulkarni, Theodorus E. Standaert, Tenko Yamashita | 2014-01-28 |
| 8637908 | Borderless contacts in semiconductor devices | Su Chen Fan, David V. Horak | 2014-01-28 |
| 8637406 | Image transfer process employing a hard mask layer | Ryan O. Jung, Yunpeng Yin | 2014-01-28 |
| 8637384 | FinFET parasitic capacitance reduction using air gap | Takashi Ando, Josephine B. Chang, Pranita Kulkarni, Theodorus E. Standaert, Tenko Yamashita | 2014-01-28 |
| 8614486 | Low resistance source and drain extensions for ETSOI | Balasubramanian S. Haran, Hemanth Jagannathan, Sanjay C. Mehta | 2013-12-24 |
| 8586482 | Film stack including metal hardmask layer for sidewall image transfer fin field effect transistor formation | John C. Arnold, Stefan Schmitz, Yunpeng Yin | 2013-11-19 |
| 8586478 | Method of making a semiconductor device | Eiichi Soda, Yunpeng Yin | 2013-11-19 |
| 8580692 | Film stack including metal hardmask layer for sidewall image transfer fin field effect transistor formation | John C. Arnold, Stefan Schmitz, Yunpeng Yin | 2013-11-12 |
| 8563225 | Forming a self-aligned hard mask for contact to a tunnel junction | Solomon Assefa | 2013-10-22 |
| 8541275 | Single metal gate CMOS integration by intermixing polarity specific capping layers | Hemanth Jagannathan, Matthew W. Copel | 2013-09-24 |
| 8518824 | Self aligning via patterning | John C. Arnold, Sean D. Burns, Yunpeng Yin | 2013-08-27 |
| 8492270 | Structure for nano-scale metallization and method for fabricating same | Shom Ponoth, David V. Horak, Elbert E. Huang, Charles W. Koburger, III, Chih-Chao Yang | 2013-07-23 |
| 8486778 | Low resistance source and drain extensions for ETSOI | Balasubramanian S. Haran, Hemanth Jagannathan, Sanjay C. Mehta | 2013-07-16 |
| 8455364 | Sidewall image transfer using the lithographic stack as the mandrel | — | 2013-06-04 |
| 8420464 | Spacer as hard mask scheme for in-situ doping in CMOS finFETs | Veeraraghavan S. Basker, Kangguo Cheng, Bruce B. Doris, Johnathan E. Faltermeier, Hemant Adhikari | 2013-04-16 |