Issued Patents All Time
Showing 176–200 of 204 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8421139 | Structure and method to integrate embedded DRAM with finfet | Hemanth Jagannathan, Geng Wang | 2013-04-16 |
| 8394684 | Structure and method for stress latching in non-planar semiconductor devices | Hemanth Jagannathan, Sanjay C. Mehta | 2013-03-12 |
| 8377795 | Cut first methodology for double exposure double etch integration | Veeraraghavan S. Basker, Balasubramanian S. Haran | 2013-02-19 |
| 8358012 | Metal semiconductor alloy structure for low contact resistance | Balasubramanian S. Haran | 2013-01-22 |
| 8298943 | Self aligning via patterning | John C. Arnold, Sean D. Burns, Yunpeng Yin | 2012-10-30 |
| 8164128 | Magnetic devices and techniques for formation thereof | Michael C. Gaidis | 2012-04-24 |
| 8133746 | Method for semiconductor gate hardmask removal and decoupling of implants | Hemanth Jagannathan | 2012-03-13 |
| 8124525 | Method of forming self-aligned local interconnect and structure formed thereby | Charles W. Koburger, III, David V. Horak, Shom Pomoth, Chih-Chao Yang, Su Chen Fan | 2012-02-28 |
| 8120946 | Stacked magnetic devices | Yu Lu, Michael C. Gaidis | 2012-02-21 |
| 7943458 | Methods for obtaining gate stacks with tunable threshold voltage and scaling | Hemanth Jagannathan, Matthew W. Copel | 2011-05-17 |
| 7935637 | Resist stripping methods using backfilling material layer | Nicholas C. M. Fuller, Ying Zhang | 2011-05-03 |
| 7919379 | Dielectric spacer removal | Eduard A. Cartier, Rashmi Jha, Xi Li, Renee T. Mo, Vijay Narayanan +6 more | 2011-04-05 |
| 7825000 | Method for integration of magnetic random access memories with improved lithographic alignment to magnetic tunnel junctions | Solomon Assefa | 2010-11-02 |
| 7803639 | Method of forming vertical contacts in integrated circuits | Solomon Assefa, Michael C. Gaidis, John P. Hummel | 2010-09-28 |
| 7782660 | Magnetically de-coupling magnetic memory cells and bit/word lines for reducing bit selection errors | Solomon Assefa, Janusz J. Nowak, Philip L. Trouilloud | 2010-08-24 |
| 7772663 | Method and apparatus for bitline and contact via integration in magnetic random access memory arrays | Michael C. Gaidis | 2010-08-10 |
| 7723813 | Method and structure for improved alignment in MRAM integration | David W. Abraham | 2010-05-25 |
| 7642147 | Methods for removing sidewall spacers | — | 2010-01-05 |
| 7550044 | Hard mask structure for patterning of materials | Michael C. Gaidis, Eugene J. O'Sullivan | 2009-06-23 |
| 7531367 | Utilizing sidewall spacer features to form magnetic tunnel junctions in an integrated circuit | Solomon Assefa, Michael C. Gaidis, John P. Hummel, David W. Abraham | 2009-05-12 |
| 7507633 | Method and structure for improved alignment in MRAM integration | David W. Abraham | 2009-03-24 |
| 7442647 | Structure and method for formation of cladded interconnects for MRAMs | Eugene J. O'Sullivan, Michael C. Gaidis, Michael F. Lofaro | 2008-10-28 |
| 7399646 | Magnetic devices and techniques for formation thereof | Michael C. Gaidis | 2008-07-15 |
| 7381343 | Hard mask structure for patterning of materials | Michael C. Gaidis, Eugene J. O'Sullivan | 2008-06-03 |
| 7374952 | Methods of patterning a magnetic stack of a magnetic memory cell and structures thereof | Ihar Kasko, Gregory Costrini | 2008-05-20 |