Issued Patents All Time
Showing 51–75 of 223 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9337188 | Metal-insulator-metal capacitor structure | Changyok Park, Guang-Jye Shiau, Akira Ito | 2016-05-10 |
| 9337079 | Prevention of contact to substrate shorts | Nicolas Loubet, Qing Liu | 2016-05-10 |
| 9334572 | Interconnect structure and method of making same | Ya Ou, Terry A. Spooner | 2016-05-10 |
| 9332628 | Microelectronic structure including air gap | Daniel C. Edelstein, David V. Horak, Elbert E. Huang, Satyanarayana V. Nitta, Takeshi Nogami +1 more | 2016-05-03 |
| 9331177 | Semiconductor structure with deep trench thermal conduction | Kangguo Cheng, Balasubramanian Pranatharthi Haran, Junjun Li, Theodorus E. Standaert, Tenko Yamashita | 2016-05-03 |
| 9312389 | FinFET with undoped body bulk | Hemant Deshpande | 2016-04-12 |
| 9312143 | Formation of isolation surrounding well implantation | Kangguo Cheng, Theodorus E. Standaert, Tenko Yamashita | 2016-04-12 |
| 9305882 | Interconnect structures incorporating air-gap spacers | Satya V. Nitta | 2016-04-05 |
| 9275911 | Hybrid orientation fin field effect transistor and planar field effect transistor | Kangguo Cheng, Balasubramanian S. Haran, Theodorus E. Standaert, Tenko Yamashita | 2016-03-01 |
| 9269792 | Method and structure for robust finFET replacement metal gate integration | Kangguo Cheng, Raghavasimhan Sreenivasan, Theodorus E. Standaert, Tenko Yamashita | 2016-02-23 |
| 9269629 | Dummy fin formation by gas cluster ion beam | Kangguo Cheng, Balasubramanian S. Haran, Ali Khakifirooz, Theodorus E. Standaert, Tenko Yamashita | 2016-02-23 |
| 9269621 | Dual damascene dual alignment interconnect scheme | Steven J. Holmes, David V. Horak, Charles W. Koburger, III, Chih-Chao Yang | 2016-02-23 |
| 9269611 | Integrated circuits having gate cap protection and methods of forming the same | Daniel T. Pham, Xiuyu Cai, Bala Haran, Charan V. Surisetty, Jin-Wook Lee +1 more | 2016-02-23 |
| 9263391 | Interconnect structures incorporating air-gap spacers | Satya V. Nitta | 2016-02-16 |
| 9263388 | Overlay-tolerant via mask and reactive ion etch (RIE) technique | Steven J. Holmes, David V. Horak, Charles W. Koburger, III, Chih-Chao Yang | 2016-02-16 |
| 9263290 | Sub-lithographic semiconductor structures with non-constant pitch | Marc A. Bergendahl, David V. Horak, Charles W. Koburger, III, Chih-Chao Yang | 2016-02-16 |
| 9257350 | Manufacturing process for finFET device | Kangguo Cheng, Balasubramanian S. Haran, Theodorus E. Standaert, Tenko Yamashita | 2016-02-09 |
| 9257348 | Methods of forming replacement gate structures for transistors and the resulting devices | Ruilong Xie, Kisik Choi, Su Chen Fan | 2016-02-09 |
| 9252052 | Dual shallow trench isolation liner for preventing electrical shorts | Bruce B. Doris, Prasanna Khare, Qing Liu, Nicolas Loubet, Maud Vinet | 2016-02-02 |
| 9252242 | Semiconductor structure with deep trench thermal conduction | Theodorus E. Standaert, Kangguo Cheng, Junjun Li, Balasubramanian Pranatharthi Haran, Tenko Yamashita | 2016-02-02 |
| 9245965 | Uniform finFET gate height | Balasubramanian S. Haran, Sanjay C. Mehta, Ravikumar Ramachandran, Stefan Schmitz, Theodorus E. Standaert | 2016-01-26 |
| 9224607 | Dual epitaxy region integration | Kangguo Cheng, Ali Khakifirooz, Raghavasimhan Sreenivasan | 2015-12-29 |
| 9224654 | Fin capacitor employing sidewall image transfer | Kangguo Cheng, Ramachandra Divakaruni, Theodorus E. Standaert, Tenko Yamashita | 2015-12-29 |
| 9219068 | FinFET with dielectric isolation by silicon-on-nothing and method of fabrication | Kangguo Cheng, Balasubramanian S. Haran, Theodorus E. Standaert, Tenko Yamashita | 2015-12-22 |
| 9219153 | Methods of forming gate structures for FinFET devices and the resulting semiconductor products | Ruilong Xie, Juntao Li | 2015-12-22 |