Issued Patents All Time
Showing 51–75 of 93 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7732872 | Integration scheme for multiple metal gate work function structures | Kangguo Cheng, Michael P. Chudzik, Ramachandra Divakaruni, Geng Wang, Haining Yang | 2010-06-08 |
| 7728392 | SRAM device structure including same band gap transistors having gate stacks with high-K dielectrics and same work function | Haining Yang | 2010-06-01 |
| 7678658 | Structure and method for improved SRAM interconnect | Haining Yang | 2010-03-16 |
| 7586806 | SRAM active write assist method for improved operational margins | — | 2009-09-08 |
| 7542330 | SRAM with asymmetrical pass gates | Brian J. Greene, Chun-Yung Sung, Clement Wann, Ying Zhang | 2009-06-02 |
| 7515489 | SRAM having active write assist for improved operational margins | — | 2009-04-07 |
| 7466604 | SRAM voltage control for improved operational margins | Wayne F. Ellis, Randy W. Mann, David J. Wager | 2008-12-16 |
| 7355906 | SRAM cell design to improve stability | Rajiv V. Joshi, Yue Tan | 2008-04-08 |
| 7326983 | Selective silicon-on-insulator isolation structure and method | An Steegen, Maheswaran Surendra, Hsing-Jen Wann, Ying Zhang, Franz Zach | 2008-02-05 |
| 7313032 | SRAM voltage control for improved operational margins | Wayne F. Ellis, Randy W. Mann, David J. Wager | 2007-12-25 |
| 7283410 | Real-time adaptive SRAM array for high SEU immunity | Louis L. Hsu, Jack A. Mandelman, Chih-Chao Yang | 2007-10-16 |
| 7188321 | Generation of metal holes by via mutation | Ernst Demm, Pak Leung, Alexander Hirsch | 2007-03-06 |
| 6986078 | Optimization of storage and power consumption with soft error predictor-corrector | Kenneth P. Rodbell, Henry Tang, Robert Trepp | 2006-01-10 |
| 6958516 | Discriminative SOI with oxide holes underneath DC source/drain | — | 2005-10-25 |
| 6936522 | Selective silicon-on-insulator isolation structure and method | An Steegen, Maheswaran Surendra, Hsing-Jen Wann, Ying Zhang, Franz Zach | 2005-08-30 |
| 6934182 | Method to improve cache capacity of SOI and bulk | Yuen H. Chan, Louis L. Hsu, Rajiv V. Joshi | 2005-08-23 |
| 6888741 | Secure and static 4T SRAM cells in EDRAM technology | — | 2005-05-03 |
| 6876040 | Dense SRAM cells with selective SOI | Hsingjen Wann, Ying Zhang, An Steegen | 2005-04-05 |
| 6856031 | SRAM cell with well contacts and P+ diffusion crossing to ground or N+ diffusion crossing to VDD | Phung T. Nguyen | 2005-02-15 |
| 6834003 | Content addressable memory with PFET passgate SRAM cells | Fred J. Towler | 2004-12-21 |
| 6751151 | Ultra high-speed DDP-SRAM cache | Louis L. Hsu, Toshiaki Kirihata, Li-Kong Wang | 2004-06-15 |
| 6654277 | SRAM with improved noise sensitivity | Louis L. Hsu, Rajiv V. Joshi | 2003-11-25 |
| 6552941 | Method and apparatus for identifying SRAM cells having weak pull-up PFETs | Fred J. Towler | 2003-04-22 |
| 6549453 | Method and apparatus for writing operation in SRAM cells employing PFETS pass gates | — | 2003-04-15 |
| 6507511 | Secure and dense SRAM cells in EDRAM technology | John E. Barth, Jr., Subramanian S. Iyer, Babar A. Khan | 2003-01-14 |