Issued Patents All Time
Showing 76–93 of 93 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7278300 | Gas filled reactive atomic force microscope probe | Michael Sievers, Siddhartha Panda | 2007-10-09 |
| 7256399 | Non-destructive in-situ elemental profiling | Siddhartha Panda, Michael Sievers | 2007-08-14 |
| 7186660 | Silicon precursors for deep trench silicon etch processes | Siddhartha Panda | 2007-03-06 |
| 7081393 | Reduced dielectric constant spacer materials integration for high speed logic gates | Michael P. Belyansky, Joyce C. Liu, Hsing-Jen Wann, Hongwen Yan | 2006-07-25 |
| 6953724 | Self-limited metal recess for deep trench metal fill | Nikki Edleman | 2005-10-11 |
| 6903023 | In-situ plasma etch for TERA hard mask materials | Sadanand V. Deshpande, Wendy Yan, Soctt D. Allen, Arpan Mahorowala | 2005-06-07 |
| 6869542 | Hard mask integrated etch process for patterning of silicon oxide and other dielectric materials | Sadanand V. Desphande, David M. Dobuzinsky, Arpan Mahorowala, Tina Wagner | 2005-03-22 |
| 6838347 | Method for reducing line edge roughness of oxide material using chemical oxide removal | Joyce C. Liu, Wesley C. Natzle, Hongwen Yan, Bidan Zhang | 2005-01-04 |
| 6806200 | Method of improving etch uniformity in deep silicon etching | David M. Dobuzinsky, Siddhartha Panda, Rolf Weis | 2004-10-19 |
| 6656375 | Selective nitride: oxide anisotropic etch process | Michael D. Armacost, David M. Dobuzinsky, John C. Malinowski, Hung Y. Ng, Chienfan Yu | 2003-12-02 |
| 6541320 | Method to controllably form notched polysilicon gate structures | Jeffrey J. Brown, Hongwen Yan, Qingyun Yang, Chienfan Yu | 2003-04-01 |
| 6461529 | Anisotropic nitride etch process with high selectivity to oxide and photoresist layers in a damascene etch scheme | Diane C. Boyd, Stuart M. Burns, Hussein I. Hanafi, Waldemar Walter Kocon, William C. Wille | 2002-10-08 |
| 6355567 | Retrograde openings in thin films | Scott D. Halle, Paul C. Jamison, David E. Kotecki | 2002-03-12 |
| 6345399 | Hard mask process to prevent surface roughness for selective dielectric etching | Paul C. Jamison, Tina Wagner, Hongwen Yan | 2002-02-12 |
| 6342722 | Integrated circuit having air gaps between dielectric and conducting lines | Michael D. Armacost, Peter D. Hoh, David V. Horak | 2002-01-29 |
| 6228279 | High-density plasma, organic anti-reflective coating etch system compatible with sensitive photoresist materials | Michael D. Armacost, Peter D. Hoh, Wendy Yan | 2001-05-08 |
| 6090722 | Process for fabricating a semiconductor structure having a self-aligned spacer | Michael D. Armacost, Sandra G. Malhotra, Tina Wagner | 2000-07-18 |
| 6051504 | Anisotropic and selective nitride etch process for high aspect ratio features in high density plasma | Michael D. Armacost | 2000-04-18 |