Issued Patents All Time
Showing 1,951–1,975 of 2,819 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9508587 | Formation of isolation surrounding well implantation | Shom Ponoth, Theodorus E. Standaert, Tenko Yamashita | 2016-11-29 |
| 9502673 | Transistor devices with tapered suspended vertical arrays of carbon nanotubes | Qing Cao, Zhengwen Li, Fei Liu, Zhen Zhang | 2016-11-22 |
| 9502418 | Semiconductor devices with sidewall spacers of equal thickness | Balasubramanian Pranatharthiharan, Soon-Cheon Seo | 2016-11-22 |
| 9502405 | Semiconductor device with authentication code | Qing Cao, Zhengwen Li, Fei Liu | 2016-11-22 |
| 9502309 | Forming CMOSFET structures with different contact liners | Zuoguang Liu, Tenko Yamashita | 2016-11-22 |
| 9502245 | Elimination of defects in long aspect ratio trapping trench structures | Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek | 2016-11-22 |
| 9502243 | Multi-orientation SOI substrates for co-integration of different conductivity type semiconductor devices | Bruce B. Doris, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek | 2016-11-22 |
| 9496401 | III-V device structure with multiple threshold voltage | Keith E. Fogel, Pouya Hashemi, Alexander Reznicek | 2016-11-15 |
| 9496400 | FinFET with stacked faceted S/D epitaxy for improved contact resistance | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2016-11-15 |
| 9496373 | Damage-resistant fin structures and FinFET CMOS | Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek | 2016-11-15 |
| 9496356 | Under-spacer doping in fin-based semiconductor devices | Veeraraghavan S. Basker, Ali Khakifirooz, Charles W. Koburger, III | 2016-11-15 |
| 9496343 | Secondary use of aspect ratio trapping holes as eDRAM structure | Bruce B. Doris, Ali Khakifirooz, Alexander Reznicek | 2016-11-15 |
| 9496341 | Silicon germanium fin | Judson R. Holt, Shogo Mochizuki | 2016-11-15 |
| 9496282 | Structure and method to reduce crystal defects in epitaxial fin merge using nitride deposition | Thomas N. Adam, Ali Khakifirooz, Alexander Reznicek, Raghavasimhan Sreenivasan | 2016-11-15 |
| 9496260 | Tall strained high percentage silicon germanium fins for CMOS | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2016-11-15 |
| 9496258 | Semiconductor fin isolation by a well trapping fin portion | Henry K. Utomo, Ramachandra Divakaruni, Ravikumar Ramachandran, Huiling Shang, Reinaldo Vega | 2016-11-15 |
| 9490253 | Gate planarity for finFET using dummy polish stop | Veeraraghavan S. Basker, Theodorus E. Standaert, Junli Wang | 2016-11-08 |
| 9490252 | MIM capacitor formation in RMG module | Veeraraghavan S. Basker, Theodorus E. Standaert, Junli Wang | 2016-11-08 |
| 9490223 | Structure to prevent deep trench moat charging and moat isolation fails | Joseph Ervin, Juntao Li, Chengwen Pei, Geng Wang | 2016-11-08 |
| 9484464 | Structure and method for adjusting threshold voltage of the array of transistors | Jin Cai, Robert H. Dennard, Ali Khakifirooz, Tak H. Ning | 2016-11-01 |
| 9484439 | III-V fin on insulator | Hemanth Jagannathan, Alexander Reznicek | 2016-11-01 |
| 9484405 | Stacked nanowire devices formed using lateral aspect ratio trapping | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2016-11-01 |
| 9484359 | MOSFET with work function adjusted metal backgate | Bruce B. Doris, Pranita Kerber, Ali Khakifirooz | 2016-11-01 |
| 9484348 | Structure and method to increase contact area in unmerged EPI integration for CMOS FinFETs | Veeraraghavan S. Basker, Ali Khakifirooz | 2016-11-01 |
| 9484347 | FinFET CMOS with Si NFET and SiGe PFET | Ramachandra Divakaruni, Jeehwan Kim | 2016-11-01 |