Issued Patents All Time
Showing 1,901–1,925 of 2,819 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9558991 | Formation of isolation surrounding well implantation | Shom Ponoth, Theodorus E. Standaert, Tenko Yamashita | 2017-01-31 |
| 9558950 | Overhang hardmask to prevent parasitic epitaxial nodules at gate end during source drain epitaxy | Pouya Hashemi, Shogo Mochizuki, Alexander Reznicek | 2017-01-31 |
| 9559119 | High voltage metal oxide semiconductor field effect transistor integrated into extremely thin semiconductor on insulator process | Bruce B. Doris, Ali Khakifirooz, Ghavam G. Shahidi | 2017-01-31 |
| 9559120 | Porous silicon relaxation medium for dislocation free CMOS devices | Ramachandra Divakaruni, Jeehwan Kim, Juntao Li, Devendra K. Sadana | 2017-01-31 |
| 9559014 | Self-aligned punch through stopper liner for bulk FinFET | Veeraraghavan S. Basker, Theodorus E. Standaert, Junli Wang | 2017-01-31 |
| 9559013 | Stacked nanowire semiconductor device | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2017-01-31 |
| 9559009 | Gate structure cut after formation of epitaxial active regions | Xiuyu Cai, Johnathan E. Faltermeier, Ali Khakifirooz, Theodorus E. Standaert, Ruilong Xie | 2017-01-31 |
| 9559000 | Hybrid logic and SRAM contacts | Veeraraghavan S. Basker, Ali Khakifirooz | 2017-01-31 |
| 9553032 | Fin field effect transistor including asymmetric raised active regions | Veeraraghavan S. Basker, Ali Khakifirooz | 2017-01-24 |
| 9553088 | Forming semiconductor device with close ground rules | Veeraraghavan S. Basker, Theodorus E. Standaert, Junli Wang | 2017-01-24 |
| 9548385 | Self-aligned contacts for vertical field effect transistors | Wilfried E. Haensch, Ali Khakifirooz, Davood Shahrjerdi | 2017-01-17 |
| 9548213 | Dielectric isolated fin with improved fin profile | Bruce B. Doris, Darsen D. Lu, Ali Khakifirooz, Kern Rim | 2017-01-17 |
| 9548386 | Structure and method for compressively strained silicon germanium fins for pFET devices and tensily strained silicon fins for nFET devices | Bruce B. Doris, Ali Khakifirooz, Darsen D. Lu, Alexander Reznicek, Kern Rim | 2017-01-17 |
| 9548356 | Shallow trench isolation structures | Bruce B. Doris, Balasubramanian S. Haran, Ali Khakifirooz, Pranita Kerber, Arvind Kumar +1 more | 2017-01-17 |
| 9543426 | Semiconductor devices with self-aligned contacts and low-k spacers | Ruilong Xie, Xiuyu Cai, Ali Khakifirooz | 2017-01-10 |
| 9543323 | Strain release in PFET regions | Bruce B. Doris, Ali Khakifirooz, Darsen D. Lu, Alexander Reznicek, Kern Rim | 2017-01-10 |
| 9543440 | High density vertical nanowire stack for field effect transistor | Ali Khakifirooz, Juntao Li | 2017-01-10 |
| 9543302 | Forming IV fins and III-V fins on insulator | Bruce B. Doris, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek | 2017-01-10 |
| 9536979 | FinFET with reduced capacitance | Veeraraghavan S. Basker, Ali Khakifirooz, Charles W. Koburger, III | 2017-01-03 |
| 9537011 | Partially dielectric isolated fin-shaped field effect transistor (FinFET) | Ramachandra Divakaruni, Johnathan E. Faltermeier, Edward J. Nowak, Kern Rim | 2017-01-03 |
| 9536744 | Enabling large feature alignment marks with sidewall image transfer patterning | Sivananda K. Kanakasabapathy, Fee Li Lie, Eric R. Miller, Jeffrey C. Shearer, John R. Sporre +1 more | 2017-01-03 |
| 9536789 | Fin-double-gated junction field effect transistor | Tak H. Ning | 2017-01-03 |
| 9536836 | MIS (Metal-Insulator-Semiconductor) contact structures for semiconductor devices | Ruilong Xie, Xiuyu Cai, Ali Khakifirooz | 2017-01-03 |
| 9536877 | Methods of forming different spacer structures on integrated circuit products having differing gate pitch dimensions and the resulting products | Xiuyu Cai, Ruilong Xie, Ali Khakifirooz | 2017-01-03 |
| 9536939 | High density vertically integrated FEOL MIM capacitor | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2017-01-03 |