Issued Patents All Time
Showing 1,976–2,000 of 2,819 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9484306 | MOSFET with asymmetric self-aligned contact | Xin Miao, Ruilong Xie, Tenko Yamashita | 2016-11-01 |
| 9484264 | Field effect transistor contacts | Veeraraghavan S. Basker, Theodorus E. Standaert, Junli Wang | 2016-11-01 |
| 9484267 | Stacked nanowire devices | Ramachandra Divakaruni, Juntao Li | 2016-11-01 |
| 9484266 | Complementary heterogeneous MOSFET using global SiGe substrate and hard-mask memorized germanium dilution for nFET | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2016-11-01 |
| 9478658 | Device and method for fabricating thin semiconductor channel and buried strain memorization layer | Bruce B. Doris, Ali Khakifirooz, Pranita Kulkarni, Ghavam G. Shahidi | 2016-10-25 |
| 9478600 | Method of forming substrate contact for semiconductor on insulator (SOI) substrate | Geng Wang, Roger A. Booth, Jr., Joseph Ervin, Chengwen Pei, Ravi M. Todi | 2016-10-25 |
| 9478549 | FinFET with dielectric isolation by silicon-on-nothing and method of fabrication | Balasubramanian S. Haran, Shom Ponoth, Theodorus E. Standaert, Tenko Yamashita | 2016-10-25 |
| 9478468 | Dual metal contact scheme for CMOS devices | Ali Khakifirooz, Alexander Reznicek, Tenko Yamashita | 2016-10-25 |
| 9472576 | Structure and method to reduce crystal defects in epitaxial fin merge using nitride deposition | Thomas N. Adam, Ali Khakifirooz, Alexander Reznicek, Raghavasimhan Sreenivasan | 2016-10-18 |
| 9472402 | Methods and structures for protecting one area while processing another area on a chip | Deok-kee Kim, Kenneth T. Settlemyer, Jr., Ramachandra Divakaruni, Carl Radens, Dirk Pfeiffer +4 more | 2016-10-18 |
| 9472446 | Methods of forming a FinFET semiconductor device with a unique gate configuration, and the resulting FinFET device | Ruilong Xie, Xiuyu Cai, Ali Khakifirooz | 2016-10-18 |
| 9472460 | Uniform depth fin trench formation | Alexander Reznicek, Ali Khakifirooz, Dominic J. Schepis, Pouya Hashemi | 2016-10-18 |
| 9472470 | Methods of forming FinFET with wide unmerged source drain EPI | Ali Khakifirooz, Alexander Reznicek, Dominic J. Schepis | 2016-10-18 |
| 9472555 | Nanosheet CMOS with hybrid orientation | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2016-10-18 |
| 9472558 | Semiconductor structures with stacked non-planar field effect transistors and methods of forming the structures | Ali Khakifirooz, Carl Radens, Robert C. Wong | 2016-10-18 |
| 9472573 | Silicon-germanium fin formation | Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek | 2016-10-18 |
| 9472616 | Undercut insulating regions for silicon-on-insulator device | Bruce B. Doris, Balasubramanian Pranatharthiharan, Shom Ponoth, Theodorus E. Standaert, Tenko Yamashita | 2016-10-18 |
| 9472628 | Heterogeneous source drain region and extension region | Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek | 2016-10-18 |
| 9472671 | Method and structure for forming dually strained silicon | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2016-10-18 |
| 9466755 | MIS-IL silicon solar cell with passivation layer to induce surface inversion | Qing Cao, Zhengwen Li, Fei Liu, Zhen Zhang | 2016-10-11 |
| 9466702 | Semiconductor device including multiple fin heights | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2016-10-11 |
| 9466690 | Precisely controlling III-V height | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2016-10-11 |
| 9466672 | Reduced defect densities in graded buffer layers by tensile strained interlayers | Keith E. Fogel, Pouya Hashemi, John A. Ott, Alexander Reznicek | 2016-10-11 |
| 9466570 | MOSFET with asymmetric self-aligned contact | Xin Miao, Ruilong Xie, Tenko Yamashita | 2016-10-11 |
| 9466567 | Nanowire compatible E-fuse | Bruce B. Doris, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek | 2016-10-11 |