Issued Patents All Time
Showing 2,001–2,025 of 2,819 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9461169 | Device and method for fabricating thin semiconductor channel and buried strain memorization layer | Bruce B. Doris, Ali Khakifirooz, Pranita Kulkarni, Ghavam G. Shahidi | 2016-10-04 |
| 9461146 | Overhang hardmask to prevent parasitic epitaxial nodules at gate end during source drain epitaxy | Pouya Hashemi, Shogo Mochizuki, Alexander Reznicek | 2016-10-04 |
| 9461042 | Sublithographic width finFET employing solid phase epitaxy | Joseph Ervin, Juntao Li, Chengwen Pei, Ravi M. Todi, Geng Wang | 2016-10-04 |
| 9455336 | SiGe and Si FinFET structures and methods for making the same | Bruce B. Doris, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek | 2016-09-27 |
| 9455331 | Method and structure of forming controllable unmerged epitaxial material | Xiuyu Cai, Ali Khakifirooz, Ruilong Xie, Tenko Yamashita | 2016-09-27 |
| 9455330 | Recessing RMG metal gate stack for forming self-aligned contact | Xiuyu Cai, Ali Khakifirooz, Ruilong Xie | 2016-09-27 |
| 9455323 | Under-spacer doping in fin-based semiconductor devices | Veeraraghavan S. Basker, Ali Khakifirooz, Charles W. Koburger, III | 2016-09-27 |
| 9455314 | Y-FET with self-aligned punch-through-stop (PTS) doping | Ramachandra Divakaruni, Juntao Li | 2016-09-27 |
| 9455250 | Distributed decoupling capacitor | Ali Khakifirooz, Darsen D. Lu, Ghavam G. Shahidi | 2016-09-27 |
| 9450095 | Single spacer for complementary metal oxide semiconductor process flow | Marc A. Bergendahl, Jessica Dechene, Fee Li Lie, Eric R. Miller, Jeffrey C. Shearer +2 more | 2016-09-20 |
| 9450079 | FinFET having highly doped source and drain regions | Ali Khakifirooz, Alexander Reznicek, Dominic J. Schepis | 2016-09-20 |
| 9443982 | Vertical transistor with air gap spacers | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2016-09-13 |
| 9443977 | FinFET with reduced source and drain resistance | Juntao Li, Xin Miao, Junli Wang | 2016-09-13 |
| 9443948 | Gate-all-around nanowire MOSFET and method of formation | Bruce B. Doris, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek | 2016-09-13 |
| 9443853 | Minimizing shorting between FinFET epitaxial regions | Balasubramanian Pranatharthiharan, Alexander Reznicek, Charan V. Surisetty | 2016-09-13 |
| 9437680 | Silicon-on-insulator substrates having selectively formed strained and relaxed device regions | Bruce B. Doris, Ali Khakifirooz, Devendra K. Sadana | 2016-09-06 |
| 9437679 | Semi-conductor device with epitaxial source/drain facetting provided at the gate edge | Thomas N. Adam, Bruce B. Doris, Ali Khakifirooz, Alexander Reznicek | 2016-09-06 |
| 9437675 | eDRAM for planar III-V semiconductor devices | Bruce B. Doris, Ali Khakifirooz, Alexander Reznicek | 2016-09-06 |
| 9437502 | Method to form stacked germanium nanowires and stacked III-V nanowires | Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek | 2016-09-06 |
| 9437501 | Stacked nanowire device width adjustment by gas cluster ion beam (GCIB) | Xin Miao, Ruilong Xie, Tenko Yamashita | 2016-09-06 |
| 9431523 | Local thinning of semiconductor fins | Ramachandra Divakaruni, Carl Radens | 2016-08-30 |
| 9431521 | Stress memorization technique for strain coupling enhancement in bulk finFET device | Juntao Li, Chun-Chen Yeh | 2016-08-30 |
| 9431425 | Directly forming SiGe fins on oxide | Hong He, Juntao Li, Junli Wang | 2016-08-30 |
| 9431306 | Methods of forming fin isolation regions on FinFET semiconductor devices using an oxidation-blocking layer of material and by performing a fin-trimming process | Ajey Poovannummoottil Jacob, Bruce B. Doris, Ali Khakifirooz, Kern Rim | 2016-08-30 |
| 9431296 | Structure and method to form liner silicide with improved contact resistance and reliablity | Veeraraghavan S. Basker, Ali Khakifirooz | 2016-08-30 |