Issued Patents All Time
Showing 1,026–1,050 of 2,819 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10332961 | Inner spacer for nanosheet transistors | Ruilong Xie, Tenko Yamashita, Chun-Chen Yeh | 2019-06-25 |
| 10332880 | Vertical fin resistor devices | Zhenxing Bi, Peng Xu | 2019-06-25 |
| 10332802 | Hybrid-channel nano-sheets FETs | Zhenxing Bi, Peng Xu, Wenyu Xu | 2019-06-25 |
| 10332800 | Vertical field effect transistor having U-shaped top spacer | Xin Miao, Wenyu Xu, Chen Zhang | 2019-06-25 |
| 10332799 | Vertical silicon/silicon-germanium transistors with multiple threshold voltages | Zhenxing Bi, Juntao Li, Peng Xu | 2019-06-25 |
| 10332796 | Fin pitch scaling for high voltage devices and low voltage devices on the same wafer | Veeraraghavan S. Basker, Theodorus E. Standaert, Junli Wang | 2019-06-25 |
| 10332983 | Vertical field-effect transistors including uniform gate lengths | Choonghyun Lee, Juntao Li, Heng Wu, Peng Xu | 2019-06-25 |
| 10326022 | Self-aligned gate cut with polysilicon liner oxidation | Peng Xu | 2019-06-18 |
| 10326020 | Structure and method for forming strained FinFET by cladding stressors | Juntao Li | 2019-06-18 |
| 10326019 | Fully-depleted CMOS transistors with U-shaped channel | Robert H. Dennard, Bruce B. Doris, Terence B. Hook | 2019-06-18 |
| 10326017 | Formation of a bottom source-drain for vertical field-effect transistors | Marc A. Bergendahl, Fee Li Lie, Shogo Mochizuki, Junli Wang | 2019-06-18 |
| 10325999 | Contact area to trench silicide resistance reduction by high-resistance interface removal | Veeraraghavan S. Basker, Theodorus E. Standaert, Junli Wang | 2019-06-18 |
| 10325995 | Field effect transistor air-gap spacers with an etch-stop layer | Xin Miao, Wenyu Xu, Chen Zhang | 2019-06-18 |
| 10325817 | Semiconductor fin patterning techniques to achieve uniform fin profiles for fin field effect transistors | Zhenxing Bi, Juntao Li, Peng Xu | 2019-06-18 |
| 10319731 | Integrated circuit structure having VFET and embedded memory structure and method of forming same | Ruilong Xie, Chun-Chen Yeh, Tenko Yamashita | 2019-06-11 |
| 10319717 | Forming on-chip metal-insulator-semiconductor capacitor with pillars | Zhenxing Bi, Peng Xu, Chen Zhang | 2019-06-11 |
| 10319677 | Fabrication of vertical fuses from vertical fins | James J. Demarest, Juntao Li | 2019-06-11 |
| 10319645 | Method for forming a semiconductor structure containing high mobility semiconductor channel materials | Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek | 2019-06-11 |
| 10319643 | Vertical FET with strained channel | Choonghyun Lee, Juntao Li, Shogo Mochizuki | 2019-06-11 |
| 10319640 | FinFET devices | Veeraraghavan S. Basker, Theodorus E. Standaert, Junli Wang | 2019-06-11 |
| 10319638 | Self-aligned contact cap | Peng Xu | 2019-06-11 |
| 10319813 | Nanosheet CMOS transistors | Zhenxing Bi, Juntao Li, Peng Xu | 2019-06-11 |
| 10312370 | Forming a sacrificial liner for dual channel devices | Huiming Bu, Dechao Guo, Sivananda K. Kanakasabapathy, Peng Xu | 2019-06-04 |
| 10312350 | Nanosheet with changing SiGe percentage for SiGe lateral recess | Xin Miao, Wenyu Xu, Chen Zhang | 2019-06-04 |
| 10312337 | Fabrication of nano-sheet transistors with different threshold voltages | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2019-06-04 |