Issued Patents All Time
Showing 76–100 of 2,819 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12107014 | Nanosheet transistors with self-aligned gate cut | Julien Frougier, Huimei Zhou, Ruilong Xie, Chanro Park | 2024-10-01 |
| 12106969 | Substrate thinning for a backside power distribution network | Ruilong Xie, Balasubramanian Pranatharthiharan, Mukta G. Farooq, Julien Frougier, Takeshi Nogami +1 more | 2024-10-01 |
| 12094972 | Gate-all-around field effect transistors having end portions of nanosheet channel layers adjacent to source/drain regions being wider than the center portions | Julien Frougier, Ruilong Xie, Chanro Park | 2024-09-17 |
| 12094949 | Fin-type field effect transistor having a wrap-around gate with bottom isolation and inner spacers to reduce parasitic capacitance | Choonghyun Lee, Chanro Park, Ruilong Xie | 2024-09-17 |
| 12087770 | Complementary field effect transistor devices | Ruilong Xie, Julien Frougier, Heng Wu, Chen Zhang | 2024-09-10 |
| 12087691 | Semiconductor structures with backside gate contacts | Ruilong Xie, Julien Frougier, Veeraraghavan S. Basker, Lawrence A. Clevenger, Nicolas Loubet +3 more | 2024-09-10 |
| 12080714 | Buried local interconnect between complementary field-effect transistor cells | Ruilong Xie, Reinaldo Vega, Alexander Reznicek | 2024-09-03 |
| 12046643 | Semiconductor structures with power rail disposed under active gate | Julien Frougier, Ruilong Xie, Chanro Park | 2024-07-23 |
| 12027224 | Authenticity and yield by reading defective cells | Julien Frougier, Ruilong Xie | 2024-07-02 |
| 12002850 | Nanosheet-based semiconductor structure with dielectric pillar | Julien Frougier, Ruilong Xie, Chanro Park | 2024-06-04 |
| 12002808 | Dual dielectric pillar fork sheet device | Ruilong Xie, Julien Frougier, Dimitri Houssameddine | 2024-06-04 |
| 12002753 | Electronic fuse with passive two-terminal phase change material and method of fabrication | Kevin W. Brew, Lan Yu, Ruilong Xie | 2024-06-04 |
| 11996480 | Vertical transistor with late source/drain epitaxy | Juntao Li, Shogo Mochizuki, Choonghyun Lee | 2024-05-28 |
| 11978796 | Contact and isolation in monolithically stacked VTFET | Chen Zhang, Ruilong Xie, Lan Yu | 2024-05-07 |
| 11978783 | Vertical fin field effect transistor devices with reduced top source/drain variability and lower resistance | Shogo Mochizuki, Choonghyun Lee, Juntao Li | 2024-05-07 |
| RE49954 | Fabrication of nano-sheet transistors with different threshold voltages | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2024-04-30 |
| 11963774 | Method probe with high density electrodes, and a formation thereof | — | 2024-04-23 |
| 11963469 | Phase change memory cell with an airgap to allow for the expansion and restriction of the PCM material | Ruilong Xie, Carl Radens, Juntao Li | 2024-04-16 |
| 11963456 | MRAM memory array yield improvement | Dimitri Houssameddine, Julien Frougier, Ruilong Xie | 2024-04-16 |
| 11961544 | Spin-orbit torque (SOT) magnetoresistive random-access memory (MRAM) with low resistivity spin hall effect (SHE) write line | Julien Frougier, Dimitri Houssameddine, Ruilong Xie | 2024-04-16 |
| 11955526 | Thick gate oxide device option for nanosheet device | Ruilong Xie, Julien Frougier, Chanro Park, Veeraraghavan S. Basker | 2024-04-09 |
| 11942374 | Nanosheet field effect transistor with a source drain epitaxy replacement | Ruilong Xie, Julien Frougier, Chanro Park | 2024-03-26 |
| 11937522 | Confining filament at pillar center for memory devices | Dexin Kong, Takashi Ando, Juntao Li | 2024-03-19 |
| 11937521 | Structure and method to fabricate resistive memory with vertical pre-determined filament | Chanro Park, Ruilong Xie, Choonghyun Lee | 2024-03-19 |
| 11935930 | Wrap-around-contact for 2D-channel gate-all-around field-effect-transistors | Julien Frougier, Ruilong Xie, Chanro Park, Andrew Gaul | 2024-03-19 |