Issued Patents All Time
Showing 26–50 of 94 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8928350 | Programming the behavior of individual chips or strata in a 3D stack of integrated circuits | Liang Pang, Matthew R. Wordeman | 2015-01-06 |
| 8809995 | Through silicon via noise suppression using buried interface contacts | Xiaomin Duan, Xiaoxiong Gu, Yong Liu | 2014-08-19 |
| 8587357 | AC supply noise reduction in a 3D stack with voltage sensing and clock shifting | Jae-Joon Kim, Yu-Shiang Lin, Liang Pang | 2013-11-19 |
| 8576000 | 3D chip stack skew reduction with resonant clock and inductive coupling | Jae-Joon Kim, Yu-Shiang Lin, Liang Pang | 2013-11-05 |
| 8570088 | 3D integrated circuit stack-wide synchronization circuit | Matthew R. Wordeman | 2013-10-29 |
| 8519735 | Programming the behavior of individual chips or strata in a 3D stack of integrated circuits | Liang Pang, Matthew R. Wordeman | 2013-08-27 |
| 8489863 | Processor including age tracking of issue queue instructions | James Wilson Bishop, Mary D. Brown, Jeffrey C. Brownscheidle, Robert A. Cordes, Maureen A. Delaney +2 more | 2013-07-16 |
| 8476953 | 3D integrated circuit stack-wide synchronization circuit | Matthew R. Wordeman | 2013-07-02 |
| 8476771 | Configuration of connections in a 3D stack of integrated circuits | Michael R. Scheuermann, Matthew R. Wordeman | 2013-07-02 |
| 8466739 | 3D chip stack skew reduction with resonant clock and inductive coupling | Jae-Joon Kim, Yu-Shiang Lin, Liang Pang | 2013-06-18 |
| 8380964 | Processor including age tracking of issue queue instructions | James Wilson Bishop, Mary D. Brown, Jeffrey C. Brownscheidle, Robert A. Cordes, Maureen A. Delaney +2 more | 2013-02-19 |
| 8136061 | Method of logic circuit synthesis and design using a dynamic circuit library | Sang Hoo Dhong, Harm Peter Hofstee, Stephen Douglas Posluszny, Osamu Takahashi, Dieter Wendel | 2012-03-13 |
| 8127116 | Dependency matrix with reduced area and power consumption | Saiful Islam, Mary D. Brown, Bjorn P. Christensen, Sam Gat-Shang Chu, Robert A. Cordes +2 more | 2012-02-28 |
| 7962811 | Scan chain disable function for power saving | Sang Hoo Dhong, Osamu Takahashi, James D. Warnock, Dieter Wendel | 2011-06-14 |
| 7746140 | Scannable latch | Sang Hoo Dhong, Osamu Takahashi | 2010-06-29 |
| 7689812 | Method and system for restoring register mapper states for an out-of-order microprocessor | Christopher M. Abernathy, Mary D. Brown, Dung Q. Nguyen | 2010-03-30 |
| 7493357 | Random carry-in for floating-point operations | Sang Hoo Dhong, Harm Peter Hofstee, Kevin John Nowka, Steven Douglas Posluszny | 2009-02-17 |
| 7363609 | Method of logic circuit synthesis and design using a dynamic circuit library | Sang Hoo Dhong, Harm Peter Hofstee, Stephen Douglas Posluszny, Osamu Takahashi, Dieter Wendel | 2008-04-22 |
| 7237163 | Leakage current reduction system and method | Sang Hoo Dhong, Hwa-Joon Oh, Silvia M. Mueller | 2007-06-26 |
| 7225422 | Wire trimmed programmable logic array | Robert J. Bucki, Sang Hoo Dhong, Osamu Takahashi | 2007-05-29 |
| 7170316 | Programmable logic array latch | Sang Hoo Dhong, Brian Flachs, Osamu Takahashi | 2007-01-30 |
| 7170328 | Scannable latch | Sang Hoo Dhong, Osamu Takahashi | 2007-01-30 |
| 7165006 | Scan chain disable function for power saving | Sang Hoo Dhong, Osamu Takahashi, James D. Warnock, Dieter Wendel | 2007-01-16 |
| 7079409 | Apparatus and method for power savings in high-performance CAM structures | Chiaming Chai, Michael Phan, Carmen C. Sloan | 2006-07-18 |
| 6961276 | Random access memory having an adaptable latency | Francois Ibrahim Atallah, James Norris Dieffenderfer, Jeffrey Herbert Fischer, Michael T. Fragano, Daniel Stephen Geise +5 more | 2005-11-01 |