Issued Patents All Time
Showing 76–94 of 94 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6138208 | Multiple level cache memory with overlapped L1 and L2 memory access | Sang Hoo Dhong, Harm Peter Hofstee, David Meltzer | 2000-10-24 |
| 6104213 | Domino logic circuit having a clocked precharge | Sang Hoo Dhong, Uttam Shyamalindu Ghoshal, Osamu Takahashi | 2000-08-15 |
| 6088763 | Method and apparatus for translating an effective address to a real address within a cache memory | Sang Hoo Dhong | 2000-07-11 |
| 6076140 | Set associative cache memory system with reduced power consumption | Sang Hoo Dhong, Philip G. Emma, William Robert Reohr | 2000-06-13 |
| 6065028 | Multifunctional macro | Sang Hoo Dhong | 2000-05-16 |
| 6065110 | Method and apparatus for loading an instruction buffer of a processor capable of out-of-order instruction issue | David Meltzer | 2000-05-16 |
| 6038659 | Method for using read-only memory to generate controls for microprocessor | Sang Hoo Dhong, Harm Peter Hofstee, David Meltzer | 2000-03-14 |
| 6035390 | Method and apparatus for generating and logically combining less than (LT), greater than (GT), and equal to (EQ) condition code bits concurrently with the execution of an arithmetic or logical operation | Jeffrey L. Burns, Sang Hoo Dhong, Kevin John Nowka | 2000-03-07 |
| 6021461 | Method for reducing power consumption in a set associative cache memory system | Sang Hoo Dhong, Philip G. Emma, William Robert Reohr | 2000-02-01 |
| 6014763 | At-speed scan testing | Sang Hoo Dhong, Harm Peter Hofstee, Kevin John Nowka | 2000-01-11 |
| 6003119 | Memory circuit for reordering selected data in parallel with selection of the data from the memory circuit | Sang Hoo Dhong | 1999-12-14 |
| 5964827 | High-speed binary adder | Hung C. Ngo, Sang Hoo Dhong | 1999-10-12 |
| 5953283 | Multi-port SRAM with reduced access requirements | David Meltzer | 1999-09-14 |
| 5911153 | Memory design which facilitates incremental fetch and store requests off applied base address requests | Sang Hoo Dhong, Philip G. Emma, William Robert Reohr | 1999-06-08 |
| 5881274 | Method and apparatus for performing add and rotate as a single instruction within a processor | Hung C. Ngo, Sang Hoo Dhong | 1999-03-09 |
| 5877972 | High speed incrementer with array method | Naoaki Aoki, Osamu Takahashi, Sang Hoo Dhong | 1999-03-02 |
| 5812838 | Branch history table | Sang Hoo Dhong, Perng Shyong Lin | 1998-09-22 |
| 5771268 | High speed rotator with array method | Naoaki Aoki, Osamu Takahashi, Sang Hoo Dhong | 1998-06-23 |
| 5710731 | Combined adder and decoder digital circuit | Michael Kevin Ciraula, Sang Hoo Dhong | 1998-01-20 |