Issued Patents All Time
Showing 26–50 of 93 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10418462 | Silicidation of bottom source/drain sheet using pinch-off sacrificial spacer process | Brent A. Anderson, Terence B. Hook, Fee Li Lie, Junli Wang | 2019-09-17 |
| 10347759 | Vertical FET structure | Brent A. Anderson, Fee Li Lie, Edward J. Nowak, Junli Wang | 2019-07-09 |
| 10319852 | Forming eDRAM unit cell with VFET and via capacitance | Brent A. Anderson, Xuefeng Liu, Junli Wang | 2019-06-11 |
| 10312370 | Forming a sacrificial liner for dual channel devices | Kangguo Cheng, Dechao Guo, Sivananda K. Kanakasabapathy, Peng Xu | 2019-06-04 |
| 10297506 | HDP fill with reduced void formation and spacer damage | Andrew M. Greene, Balasubramanian Pranatharthiharan, Ruilong Xie | 2019-05-21 |
| 10297667 | Fin field-effect transistor for input/output device integrated with nanosheet field-effect transistor | Chun Wing Yeung, Chen Zhang, Peng Xu, Kangguo Cheng | 2019-05-21 |
| 10276558 | Electrostatic discharge protection using vertical fin CMOS technology | Brent A. Anderson, Terence B. Hook, Xuefeng Liu, Junli Wang, Miaomiao Wang | 2019-04-30 |
| 10249754 | Precise junction placement in vertical semiconductor devices using etch stop layers | Liying Jiang, Siyuranga O. Koswatta, Junli Wang | 2019-04-02 |
| 10229905 | Electrostatic discharge devices and methods of manufacture | Junjun Li, Theodorus E. Standaert, Tenko Yamashita | 2019-03-12 |
| 10229983 | Methods and structures for forming field-effect transistors (FETs) with low-k spacers | Kangguo Cheng, Peng Xu | 2019-03-12 |
| 10224429 | Precise junction placement in vertical semiconductor devices using etch stop layers | Liying Jiang, Siyuranga O. Koswatta, Junli Wang | 2019-03-05 |
| 10211316 | Silicidation of bottom source/drain sheet using pinch-off sacrificial spacer process | Brent A. Anderson, Terence B. Hook, Fee Li Lie, Junli Wang | 2019-02-19 |
| 10157908 | Electrostatic discharge devices and methods of manufacture | Junjun Li, Theodorus E. Standaert, Tenko Yamashita | 2018-12-18 |
| 10153201 | Method for making a dipole-based contact structure to reduce the metal-semiconductor contact resistance in MOSFETs | Hui-feng Li, Vijay Narayanan, Hiroaki Niimi, Tenko Yamashita | 2018-12-11 |
| 10141426 | Vertical transistor device | Brent A. Anderson, Fee Li Lie, Shogo Mochizuki, Junli Wang | 2018-11-27 |
| 10083861 | HDP fill with reduced void formation and spacer damage | Andrew M. Greene, Balasubramanian Pranatharthiharan, Ruilong Xie | 2018-09-25 |
| 10002792 | HDP fill with reduced void formation and spacer damage | Andrew M. Greene, Balasubramanian Pranatharthiharan, Ruilong Xie | 2018-06-19 |
| 10002962 | Vertical FET structure | Brent A. Anderson, Fee Li Lie, Edward J. Nowak, Junli Wang | 2018-06-19 |
| 9991267 | Forming eDRAM unit cell with VFET and via capacitance | Brent A. Anderson, Xuefeng Liu, Junli Wang | 2018-06-05 |
| 9954101 | Precise junction placement in vertical semiconductor devices using etch stop layers | Liying Jiang, Siyuranga O. Koswatta, Junli Wang | 2018-04-24 |
| 9947748 | Dielectric isolated SiGe fin on bulk substrate | Shogo Mochizuki, Tenko Yamashita | 2018-04-17 |
| 9941175 | Dielectric isolated SiGe fin on bulk substrate | Shogo Mochizuki, Tenko Yamashita | 2018-04-10 |
| 9935003 | HDP fill with reduced void formation and spacer damage | Andrew M. Greene, Balasubramanian Pranatharthiharan, Ruilong Xie | 2018-04-03 |
| 9929057 | HDP fill with reduced void formation and spacer damage | Andrew M. Greene, Balasubramanian Pranatharthiharan, Ruilong Xie | 2018-03-27 |
| 9853127 | Silicidation of bottom source/drain sheet using pinch-off sacrificial spacer process | Brent A. Anderson, Terence B. Hook, Fee Li Lie, Junli Wang | 2017-12-26 |