Issued Patents All Time
Showing 526–550 of 1,279 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10269710 | Multi-level metallization interconnect structure | Praneet Adusumilli, Oscar van der Straten | 2019-04-23 |
| 10269698 | Binary metallization structure for nanoscale dual damascene interconnects | Oscar van der Straten, Praneet Adusumilli, Koichi Motoyama | 2019-04-23 |
| 10269652 | Vertical transistor top epitaxy source/drain and contact structure | Oleg Gluschenkov, Sanjay C. Mehta, Shogo Mochizuki | 2019-04-23 |
| 10262904 | Vertical transistor top epitaxy source/drain and contact structure | Oleg Gluschenkov, Sanjay C. Mehta, Shogo Mochizuki | 2019-04-16 |
| 10262900 | Wimpy device by selective laser annealing | Kangguo Cheng, Nicolas Loubet, Xin Miao | 2019-04-16 |
| 10256327 | Forming a fin using double trench epitaxy | Veeraraghavan S. Basker, Pouya Hashemi, Shogo Mochizuki | 2019-04-09 |
| 10256317 | Vertical transistor gated diode | Karthik Balakrishnan | 2019-04-09 |
| 10256301 | Nanosheet isolated source/drain epitaxy by surface treatment and incubation delay | — | 2019-04-09 |
| 10256230 | Co-fabrication of vertical diodes and fin field effect transistors on the same substrate | Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi | 2019-04-09 |
| 10249724 | Low resistance contact structures for trench structures | Praneet Adusumilli, Oscar van der Straten, Chih-Chao Yang | 2019-04-02 |
| 10249630 | Structure featuring ferroelectric capacitance in interconnect level for steep sub-threshold complementary metal oxide semiconductor transistors | Takashi Ando, Karthik Balakrishnan, Pouya Hashemi | 2019-04-02 |
| 10249622 | Epitaxial oxide fin segments to prevent strained semiconductor fin end relaxation | Karthik Balakrishnan, Keith E. Fogel, Sivananda K. Kanakasabapathy | 2019-04-02 |
| 10249501 | Single process for liner and metal fill | Praneet Adusumilli, Oscar van der Straten, Chih-Chao Yang | 2019-04-02 |
| 10243065 | Method of manufacturing SOI lateral Si-emitter SiGe base HBT | Pouya Hashemi, Tak H. Ning | 2019-03-26 |
| 10243044 | FinFETs with high quality source/drain structures | Kangguo Cheng, Ali Khakifirooz, Charan V. Surisetty | 2019-03-26 |
| 10243043 | Self-aligned air gap spacer for nanosheet CMOS devices | Shogo Mochizuki, Joshua M. Rubin, Junli Wang | 2019-03-26 |
| 10242990 | Structure featuring ferroelectric capacitance in interconnect level for steep sub-threshold complementary metal oxide semiconductor transistors | Takashi Ando, Karthik Balakrishnan, Pouya Hashemi | 2019-03-26 |
| 10236384 | Formation of FinFET junction | Kevin K. Chan, Pouya Hashemi, Ali Khakifirooz, John A. Ott | 2019-03-19 |
| 10236360 | Method of forming vertical transistor having dual bottom spacers | Oleg Gluschenkov, Sanjay C. Mehta, Shogo Mochizuki | 2019-03-19 |
| 10236217 | Stacked field-effect transistors (FETs) with shared and non-shared gates | Takashi Ando, Pouya Hashemi, Choonghyun Lee, Jingyun Zhang | 2019-03-19 |
| 10230005 | Four terminal stacked complementary junction field effect transistors | Karthik Balakrishnan, Bahman Hekmatshoartabari, Tak H. Ning | 2019-03-12 |
| 10229996 | Strained stacked nanowire field-effect transistors (FETs) | Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi | 2019-03-12 |
| 10229986 | Vertical transport field-effect transistor including dual layer top spacer | Hemanth Jagannathan, Choonghyun Lee, Christopher J. Waskiewicz | 2019-03-12 |
| 10229921 | Structure featuring ferroelectric capacitance in interconnect level for steep sub-threshold complementary metal oxide semiconductor transistors | Takashi Ando, Karthik Balakrishnan, Pouya Hashemi | 2019-03-12 |
| 10229917 | Thin SRAM cell having vertical transistors | Karthik Balakrishnan, Michael A. Guillorn, Pouya Hashemi | 2019-03-12 |