Issued Patents All Time
Showing 76–100 of 115 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7256136 | Self-patterning of photo-active dielectric materials for interconnect isolation | Wuping Liu, Bei Chao Zhang | 2007-08-14 |
| 7253097 | Integrated circuit system using dual damascene process | Yeow Kheng Lim, Chim Seng Seet, Tae Jong Lee, Kin Leong Pey | 2007-08-07 |
| 7247555 | Method to control dual damascene trench etch profile and trench depth uniformity | Hai Cong, Yong Kong Siew | 2007-07-24 |
| 7224060 | Integrated circuit with protective moat | Fan Zhang, Kho Liep Chok, Tae Jong Lee, Xiaomei Bu, Meng Luo +4 more | 2007-05-29 |
| 7202140 | Method to fabricate Ge and Si devices together for performance enhancement | Chew Hoe Ang, Dong Kyun Sohn | 2007-04-10 |
| 7202164 | Method of forming ultra thin silicon oxynitride for gate dielectric applications | Jinping Liu, Hwa Weng Koh, Dong Kyun Sohn | 2007-04-10 |
| 7166522 | Method of forming a relaxed semiconductor buffer layer on a substrate with a large lattice mismatch | Jin Ping Liu, Dong Kyun Sohn | 2007-01-23 |
| 7153766 | Metal barrier cap fabrication by polymer lift-off | Beichao Zhang, Wuping Liu | 2006-12-26 |
| 7094669 | Structure and method of liner air gap formation | Xiaomei Bu, Alex See, Tae Jong Lee, Fan Zhang, Yeon Kheng Lim | 2006-08-22 |
| 7084025 | Selective oxide trimming to improve metal T-gate transistor | Timothy Phua, Kheng Chok Tee | 2006-08-01 |
| 7056799 | Method of forming wing gate transistor for integrated circuits | Timothy Phua, Kheng Chok Tee | 2006-06-06 |
| 7012022 | Self-patterning of photo-active dielectric materials for interconnect isolation | Wuping Liu, Bei Chao Zhang | 2006-03-14 |
| 6995078 | Method of forming a relaxed semiconductor buffer layer on a substrate with a large lattice mismatch | Jin Ping Liu, Dong Kyun Sohn | 2006-02-07 |
| 6787452 | Use of amorphous carbon as a removable ARC material for dual damascene fabrication | John Sudijono, Liu Huang | 2004-09-07 |
| 6762085 | Method of forming a high performance and low cost CMOS device | Jia Zhen Zheng, Soh Yun Siah, Eng Hua Lim, Simon Chooi, Chew Hoe Ang | 2004-07-13 |
| 6586314 | Method of forming shallow trench isolation regions with improved corner rounding | Soh Yun Siah, Jia Zhen Zheng, Chew Hoe Ang | 2003-07-01 |
| 6452235 | Floating body ESD protection circuit | — | 2002-09-17 |
| 6274517 | Method of fabricating an improved spacer | — | 2001-08-14 |
| 6162724 | Method for forming metalization for inter-layer connections | Thomas Chang | 2000-12-19 |
| 6130573 | Voltage boosting circuit having asymmetric MOS in DRAM | — | 2000-10-10 |
| 6057576 | Inverse-T tungsten gate apparatus | Thomas Chang | 2000-05-02 |
| 6048762 | Method of fabricating embedded dynamic random access memory | H. J. Wu | 2000-04-11 |
| 6043547 | Circuit structure with an anti-reflective layer | Thomas Chang | 2000-03-28 |
| 6008515 | Stacked capacitor having improved charge storage capacity | Thomas Chang | 1999-12-28 |
| 5990523 | Circuit structure which avoids latchup effect | — | 1999-11-23 |