Issued Patents All Time
Showing 26–50 of 72 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6749970 | Method of enhancing clear field phase shift masks with border regions around phase 0 and phase 180 regions | Christopher A. Spence | 2004-06-15 |
| 6689541 | Process for forming a photoresist mask | Scott A. Bell, Christopher F. Lyons, Marina V. Plat, Ramkumar Subramanian | 2004-02-10 |
| 6675369 | Method of enhancing clear field phase shift masks by adding parallel line to phase 0 region | Christopher A. Spence | 2004-01-06 |
| 6660645 | Process for etching an organic dielectric using a silyated photoresist mask | Scott A. Bell, Christopher F. Lyons, Marina V. Plat, Ramkumar Subramanian | 2003-12-09 |
| 6641747 | Method and apparatus for determining an etch endpoint | Ercan Adem | 2003-11-04 |
| 6635409 | Method of strengthening photoresist to prevent pattern collapse | Christopher F. Lyons, Scott A. Bell, Marina V. Plat | 2003-10-21 |
| 6633083 | Barrier layer integrity test | Christy Mei-Chu Woo, Young-Chang Joo | 2003-10-14 |
| 6615400 | Optimizing dense via arrays of shrunk integrated circuit designs | — | 2003-09-02 |
| 6566214 | Method of making a semiconductor device by annealing a metal layer to form metal silicide and using the metal silicide as a hard mask to pattern a polysilicon layer | Christopher F. Lyons, Ramkumar Subramanian, Scott A. Bell, Marina V. Plat | 2003-05-20 |
| 6563221 | Connection structures for integrated circuits and processes for their formation | Scott A. Bell, Christopher F. Lyons, Marina V. Plat, Ramkumar Subramanian | 2003-05-13 |
| 6548423 | Multilayer anti-reflective coating process for integrated circuit fabrication | Marina V. Plat, Christopher F. Lyons, Scott A. Bell | 2003-04-15 |
| 6534224 | Phase shift mask and system and method for making the same | — | 2003-03-18 |
| 6528372 | Sidewall spacer definition of gates | Christopher F. Lyons | 2003-03-04 |
| 6524947 | Slotted trench dual inlaid structure and method of forming thereof | Ramkumar Subramanian, Fei Wang | 2003-02-25 |
| 6516450 | Variable design rule tool | Wiley Eugene Hill, Kurt Taylor, Chern-Jiann Lee, Rithy Hang | 2003-02-04 |
| 6514802 | Method of providing a frontside contact to a substrate of SOI device | Kurt Taylor | 2003-02-04 |
| 6479350 | Reduced masking step CMOS transistor formation using removable amorphous silicon sidewall spacers | Zicheng Gary Ling, Raymond T. Lee | 2002-11-12 |
| 6472317 | Dual damascene arrangement for metal interconnection with low k dielectric constant materials in dielectric layers | Fei Wang, Jerry Cheng, Simon S. Chan | 2002-10-29 |
| 6458606 | Etch bias distribution across semiconductor wafer | Marina V. Plat, Luigi Capodieci, Scott A. Bell | 2002-10-01 |
| 6448164 | Dark field image reversal for gate or line patterning | Christopher F. Lyons, Ramkumar Subramanian, Marina V. Plat | 2002-09-10 |
| 6383827 | Electrical alignment test structure using local interconnect ladder resistor | Asim A. Selcuk | 2002-05-07 |
| 6358856 | Bright field image reversal for contact hole patterning | Christopher F. Lyons, Ramkumar Subramanian, Marina V. Plat | 2002-03-19 |
| 6355511 | Method of providing a frontside contact to substrate of SOI device | Kurt Taylor | 2002-03-12 |
| 6350687 | Method of fabricating improved copper metallization including forming and removing passivation layer before forming capping film | Steven C. Avanzino, Kai Yang, Sergey Lopatin | 2002-02-26 |
| 6312874 | Method for forming a dual damascene trench and underlying borderless via in low dielectric constant materials | Simon S. Chan, Fei Wang | 2001-11-06 |