Issued Patents All Time
Showing 51–72 of 72 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6309955 | Method for using a CVD organic barc as a hard mask during via etch | Ramkumar Subramanian, Fei Wang, Lynne A. Okada | 2001-10-30 |
| 6291860 | Self-aligned contacts to source/drain silicon electrodes utilizing polysilicon and silicides | — | 2001-09-18 |
| 6291887 | Dual damascene arrangements for metal interconnection with low k dielectric constant materials and nitride middle etch stop layer | Fei Wang, Jerry Cheng | 2001-09-18 |
| 6279147 | Use of an existing product map as a background for making test masks | Matthew S. Buynoski, Ramkumar Subramanian | 2001-08-21 |
| 6265253 | Aluminum disposable spacer to reduce mask count in CMOS transistor formation | Matthew S. Buynoski, Zicheng Gary Ling | 2001-07-24 |
| 6262435 | Etch bias distribution across semiconductor wafer | Marina V. Plat, Luigi Capodieci, Scott A. Bell | 2001-07-17 |
| 6255735 | Dual damascene arrangement for metal interconnection with low k dielectric constant materials in dielectric layers | Fei Wang, Jerry Cheng, Simon S. Chan | 2001-07-03 |
| 6221706 | Aluminum disposable spacer to reduce mask count in CMOS transistor formation | Raymond T. Lee, Zicheng Gary Ling, Matthew S. Buynoski | 2001-04-24 |
| 6218224 | Nitride disposable spacer to reduce mask count in CMOS transistor formation | Raymond T. Lee, Zicheng Gary Ling | 2001-04-17 |
| 6217418 | Polishing pad and method for polishing porous materials | Kashmir Sahota | 2001-04-17 |
| 6211071 | Optimized trench/via profile for damascene filling | Fei Wang, Steven C. Avanzino | 2001-04-03 |
| 6184114 | MOS transistor formation | — | 2001-02-06 |
| 6156643 | Method of forming a dual damascene trench and borderless via structure | Simon S. Chan, Fei Wang | 2000-12-05 |
| 6153514 | Self-aligned dual damascene arrangement for metal interconnection with low k dielectric constant materials and nitride middle etch stop layer | Fei Wang, Jerry Cheng | 2000-11-28 |
| 6121149 | Optimized trench/via profile for damascene filling | Fei Wang, Steven C. Avanzino | 2000-09-19 |
| 6117781 | Optimized trench/via profile for damascene processing | Fei Wang, Steven C. Avanzino | 2000-09-12 |
| 6117782 | Optimized trench/via profile for damascene filling | Fei Wang, Steven C. Avanzino | 2000-09-12 |
| 6107185 | Conductive material adhesion enhancement in damascene process for semiconductors | — | 2000-08-22 |
| 6103563 | Nitride disposable spacer to reduce mask count in CMOS transistor formation | Raymond T. Lee, Zicheng Gary Ling | 2000-08-15 |
| 6096644 | Self-aligned contacts to source/drain silicon electrodes utilizing polysilicon and metal silicides | — | 2000-08-01 |
| 6066557 | Method for fabricating protected copper metallization | Dirk Brown, Takeshi Nogami | 2000-05-23 |
| 5858844 | Method for construction and fabrication of submicron field-effect transistors by optimization of poly oxide process | Hao Fang, Farrokh Omid-Zehoor, Chris Schmidt | 1999-01-12 |