Issued Patents All Time
Showing 226–250 of 251 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6348379 | Method of forming self-aligned contacts using consumable spacers | Fei Wang, Yu Sun | 2002-02-19 |
| 6335152 | Use of RTA furnace for photoresist baking | Bharath Rangarajan, Michael K. Templeton, Bhanwar Singh | 2002-01-01 |
| 6326231 | Use of silicon oxynitride ARC for metal layers | Bhanwar Singh, Sanjay K. Yedur, Marina V. Plat, Christopher F. Lyons, Bharath Rangarajan +1 more | 2001-12-04 |
| 6322009 | Common nozzle for resist development | Khoi A. Phan, Bharath Rangarajan, Bhanwar Singh | 2001-11-27 |
| 6319643 | Conductive photoresist pattern for long term calibration of scanning electron microscope | Bhanwar Singh, Bryan K. Choo | 2001-11-20 |
| 6319802 | T-gate formation using modified damascene processing with two masks | Christopher F. Lyons, Bhanwar Singh, Marina V. Plat | 2001-11-20 |
| 6313019 | Y-gate formation using damascene processing | Christopher F. Lyons, Bhanwar Singh, Marina V. Plat | 2001-11-06 |
| 6309955 | Method for using a CVD organic barc as a hard mask during via etch | Fei Wang, Todd P. Lukanc, Lynne A. Okada | 2001-10-30 |
| 6306769 | Use of dual patterning masks for printing holes of small dimensions | Marina V. Plat | 2001-10-23 |
| 6294460 | Semiconductor manufacturing method using a high extinction coefficient dielectric photomask | Minh Van Ngo, Suzette K. Pangrle, Kashmir Sahota | 2001-09-25 |
| 6279147 | Use of an existing product map as a background for making test masks | Matthew S. Buynoski, Todd P. Lukanc | 2001-08-21 |
| 6274289 | Chemical resist thickness reduction process | Michael K. Templeton, Bharath Rangarajan, Ursula Q. Quinto | 2001-08-14 |
| 6270929 | Damascene T-gate using a relacs flow | Christopher F. Lyons, Bhanwar Singh, Marina V. Plat | 2001-08-07 |
| 6270579 | Nozzle arm movement for resist development | Khoi A. Phan, Bharath Rangarajan, Bhanwar Singh, Michael K. Templeton, Sanjay K. Yedur | 2001-08-07 |
| 6262484 | Dual damascene method for backened metallization using poly stop layers | Bharath Rangarajan, Bhanwar Singh | 2001-07-17 |
| 6255202 | Damascene T-gate using a spacer flow | Christopher F. Lyons, Bhanwar Singh, Marina V. Plat | 2001-07-03 |
| 6251570 | Resist developer saving system using material to reduce surface tension and wet resist surface | Khoi A. Phan, Bharath Rangarajan, Bhanwar Singh | 2001-06-26 |
| 6248175 | Nozzle arm movement for resist development | Khoi A. Phan, Bharath Rangarajan, Bhanwar Singh, Michael K. Templeton, Sanjay K. Yedur | 2001-06-19 |
| 6222936 | Apparatus and method for reducing defects in a semiconductor lithographic process | Khoi A. Phan, Gurjeet S. Bains, David A. Steele, Jonathan Alan Orth | 2001-04-24 |
| 6190062 | Cleaning chamber built into SEM for plasma or gaseous phase cleaning | Khoi A. Phan, Bharath Rangarajan, Bhanwar Singh, Bryan K. Choo, Sanjay K. Yedur | 2001-02-20 |
| 6191030 | Anti-reflective coating layer for semiconductor device | Suzette K. Pangrle, John G. Pellerin, Ernesto A. Gallardo | 2001-02-20 |
| 6187666 | CVD plasma process to fill contact hole in damascene process | Bhanwar Singh, Michael K. Templeton, Bharath Rangarajan, Christopher F. Lyons, Sanjay K. Yedur | 2001-02-13 |
| 6136514 | Resist developer saving system using material to reduce surface tension and wet resist surface | Khoi A. Phan, Bharath Rangarajan, Bhanwar Singh | 2000-10-24 |
| 6127089 | Interconnect structure with low k dielectric materials and method of making the same with single and dual damascene techniques | Christopher F. Lyons, Uzodinma Okoroanyanwu | 2000-10-03 |
| 6060380 | Antireflective siliconoxynitride hardmask layer used during etching processes in integrated circuit fabrication | Bhanwar Singh, Simon S. Chan, Fei Wang | 2000-05-09 |