Issued Patents All Time
Showing 126–150 of 205 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6562717 | Semiconductor device having multiple thickness nickel silicide layers | Christy Mei-Chu Woo, George Jonathan Kluth | 2003-05-13 |
| 6562718 | Process for forming fully silicided gates | Ercan Adem, Jacques Bertrand, Paul R. Besser, Matthew S. Buynoski, John Foster +5 more | 2003-05-13 |
| 6555879 | SOI device with metal source/drain and method of fabrication | Zoran Krivokapic, Bin Yu | 2003-04-29 |
| 6555453 | Fully nickel silicided metal gate with shallow junction formed | Christy Mei-Chu Woo, George Jonathan Kluth | 2003-04-29 |
| 6555439 | Partial recrystallization of source/drain region before laser thermal annealing | Robert B. Ogle, Eric N. Paton, Cyrus E. Tabery, Bin Yu | 2003-04-29 |
| 6551888 | Tuning absorption levels during laser thermal annealing | Cyrus E. Tabery, Eric N. Paton, Bin Yu, Robert B. Ogle | 2003-04-22 |
| 6544872 | Dopant implantation processing for improved source/drain interface with metal silicides | Matthew S. Buynoski, George Jonathan Kluth | 2003-04-08 |
| 6534822 | Silicon on insulator field effect transistor with a double Schottky gate structure | Matthew S. Buynoski | 2003-03-18 |
| 6528858 | MOSFETs with differing gate dielectrics and method of formation | Bin Yu, Olov Karlsson, Haihong Wang, Zoran Krivokapic | 2003-03-04 |
| 6528362 | Metal gate with CVD amorphous silicon layer for CMOS devices and method of making with a replacement gate process | Paul R. Besser, Matthew S. Buynoski | 2003-03-04 |
| 6525381 | Semiconductor-on-insulator body-source contact using shallow-doped source, and method | Wei Long, Yowjuang W. Liu | 2003-02-25 |
| 6524929 | Method for shallow trench isolation using passivation material for trench bottom liner | Philip A. Fisher | 2003-02-25 |
| 6518154 | Method of forming semiconductor devices with differently composed metal-based gate electrodes | Matthew S. Buynoski, Paul R. Besser | 2003-02-11 |
| 6518107 | Non-arsenic N-type dopant implantation for improved source/drain interfaces with nickel silicides | Matthew S. Buynoski, Paul R. Besser | 2003-02-11 |
| 6514809 | SOI field effect transistors with body contacts formed by selective etch and fill | — | 2003-02-04 |
| 6504214 | MOSFET device having high-K dielectric layer | Bin Yu | 2003-01-07 |
| 6492249 | High-K gate dielectric process with process with self aligned damascene contact to damascene gate and a low-k inter level dielectric | Matthew S. Buynoski, Ming-Ren Lin | 2002-12-10 |
| 6486038 | Method for and device having STI using partial etch trench bottom liner | Witold P. Maszara, Ming-Ren Lin | 2002-11-26 |
| 6479866 | SOI device with self-aligned selective damage implant, and method | — | 2002-11-12 |
| 6475874 | Damascene NiSi metal gate high-k transistor | Paul R. Besser, Matthew S. Buynoski, John Foster, Paul L. King, Eric N. Paton | 2002-11-05 |
| 6465334 | Enhanced electroless deposition of dielectric precursor materials for use in in-laid gate MOS transistors | Matthew S. Buynoski, Paul R. Besser, Paul L. King, Eric N. Paton | 2002-10-15 |
| 6465309 | Silicide gate transistors | Paul R. Besser, Matthew S. Buynoski, John Foster, Paul L. King, Eric N. Paton | 2002-10-15 |
| 6465267 | Method of measuring gate capacitance to determine the electrical thickness of gate dielectrics | Haihong Wang | 2002-10-15 |
| 6458679 | Method of making silicide stop layer in a damascene semiconductor structure | Eric N. Paton, Paul R. Besser, Matthew S. Buynoski, Paul L. King, John Foster | 2002-10-01 |
| 6451693 | Double silicide formation in polysicon gate without silicide in source/drain extensions | Christy Mei-Chu Woo, George Jonathan Kluth | 2002-09-17 |